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Started by Farabi, October 13, 2011, 05:22:20 AM

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Farabi

Is something like this still used on modern VGA card

#define RGB_RESET 0x03C6
#define RGB_READ  0x03C7
#define RGB_WRITE 0x03C8
#define RGB_DATA  0x03C9

void setwhite(void)
{
   outp(RGB_RESET, 0xFF);     // Prepare the VGA card
   outp(RGB_WRITE, WHITE);    // Tell that we want to write the color 15 (WHITE)
   outp(RGB_DATA, 64);        // Red value
   outp(RGB_DATA, 64);        // Green value
   outp(RGB_DATA, 64);        // Blue value
}

For setting all the 256 colors simply tell to the VGA card that we want to write the color 0, and next write the RGB of all the colors:


void setpalette(char *palette)
{
   register int i;

   outp(RGB_RESET, 0xFF); // Prepare the VGA card
   outp(RGB_WRITE, 0);                  // Tell that we want to write the entire palette
   for(i=0;i<256;i++) {
      outp(RGB_DATA, palette[i*3]);     // Red value
      outp(RGB_DATA, palette[i*3+1]);   // Green value
      outp(RGB_DATA, palette[i*3+2]);   // Blue value
   }
}



Is there any standard for the Intel IN/OUT instruction for all devices?
Those who had universe knowledges can control the world by a micro processor.
http://www.wix.com/farabio/firstpage

"Etos siperi elegi"

Tedd

Any video card should provide basic VGA support, so it should work as long as you don't try to do anything clever.


In general, you will need a separate driver for each device. Though there are a few 'standards' that will provide basic functionality for certain classes of device.
No snowflake in an avalanche feels responsible.

Farabi

I tried to Install an IRQ for the mouse driver but did not seems good. It wont jump back, and I dont know what is wrong



;Here is the Handler
;This handler is 32-bit Interupt Handler
int1:
push  0
push  1
iret


; Here is the IRQ Installer
IDTSetGate proc nInt:dword,lpStruct:dword,sel:word,flags:byte

cli

mov eax,IDT_TABLE
mov eax,[eax].IDTAddr.address
mov ecx,nInt

mov edx,lpStruct
mov [eax+ecx*8].IDTEntry.base_lo,dx
shr edx,16
mov [eax+ecx*8].IDTEntry.base_hi,dx
mov dx,sel
mov [eax+ecx*8].IDTEntry.sel,dx
mov dl,flags
mov [eax+ecx*8].IDTEntry.flags,dl
mov dl,0
mov [eax+ecx*8].IDTEntry.always0,dl

mov eax,IDT_TABLE
lidt fword ptr[eax]
sti

ret
IDTSetGate endp

;Here is the Mouse init function
MouseInstall proc
LOCAL _status:byte

invoke MouseWait,1 ;/Enable the auxiliary mouse device
mov al,0A8h
out 64h,al

invoke MouseWait,1 ;Enable the interrupts
mov al,20h
out 64h,al
invoke MouseWait,0
in al,60h
mov _status,al
invoke MouseWait,1
mov al,60h
out 64h,al
invoke MouseWait,1
mov al,_status
out 64h,al

; Tell mouse to use default setting
invoke MouseWrite,0f6h
invoke MouseRead ;

;Enable the Mouse
invoke MouseWrite,0f4h
invoke MouseRead ;
invoke IDTSetGate,12,addr MouseHandler,020h,8Eh  ; I tried to use selector for 16 bit, it wont back, I used selector for 32-bit and it wont come back too

ret
MouseInstall endp


;Here is the GDT
bcopy_gdt:
dw bcopy_gdt_size-1 ; Null descriptor - contains GDT
dd bcopy_gdt ; pointer for LGDT instruction
dw 0

; TSS segment to keep Intel VT happy.  Intel VT is
; unhappy about anything that doesn't smell like a
; full-blown 32-bit OS.
desc TSS
dw 104-1, DummyTSS ; 08h 32-bit task state segment
dd 00008900h ; present, dpl 0, 104 bytes @DummyTSS

desc CS16
dd 0000ffffh ; 10h Code segment, use16, readable,
dd 00009b00h ; present, dpl 0, cover 64K
desc DS16
dd 0000ffffh ; 18h Data segment, use16, read/write,
dd 00009300h ; present, dpl 0, cover 64K
desc CS32
dd 0000ffffh ; 20h Code segment, use32, readable,
dd 00cf9b00h ; present, dpl 0, cover all 4G
desc DS32
dd 0000ffffh ; 28h Data segment, use32, read/write,
dd 00cf9300h ; present, dpl 0, cover all 4G

bcopy_gdt_size: equ $-bcopy_gdt
Those who had universe knowledges can control the world by a micro processor.
http://www.wix.com/farabio/firstpage

"Etos siperi elegi"

dedndave

#3
first, interrupt 1 is the single-step interrupt

http://stanislavs.org/helppc/int_table.html

second, you should push the flags, then CS, then the return IP - at least that's how 16-bit interrupts work

this looks like crazy code to me - lol
int1:   push  0
        push  1
        iret


when an interrupt occurs, the interrupt flag is cleared automatically
for hardware interrupts, the PIC (programmable interrupt controller) must be cleared before other interrupts can be handled
this is done by sending the PIC an "EOI", which - i forget, but i think it's OUT 20h,20h

at the end of the handler routine, you need an IRET

i have never tried a 32-bit interrupt handler, but i am sure there is all kinds of priviledge level stuff going on   :bg

EDIT: not even sure there is such a thing as a 32-bit interrupt   :bg

http://forum.osdev.org/

Tedd

Farabi, please do yourself (and us) a favour and DO YOUR BACKGROUND READING. Then you might actually understand what you're doing and you won't have these problems. It's quite clear you're just hacking around trying to make things work - you will save yourself a lot of time and confusion by reading the material that tells you all of the answers.

1. Read the intel software developer's manuals - specifically volume 3 "System Programming Guide"
2. Browse and read the relevant articles on http://wiki.osdev.org/Main_Page
3. Read the intel manuals again
4. Rewrite everything you've already written

I know this seems like the long way around, and if you can just get this part to work the rest will be easy. It won't. It's a hard subject and there isn't a shortcut (other than tweaking an already working OS.)
There is no point trying to help you when you don't even understand what's going on.
No snowflake in an avalanche feels responsible.

Farabi

Those who had universe knowledges can control the world by a micro processor.
http://www.wix.com/farabio/firstpage

"Etos siperi elegi"

Farabi

Haha I got it working  :cheekygreen:
It is simpler than I though, I should just read it better.
Those who had universe knowledges can control the world by a micro processor.
http://www.wix.com/farabio/firstpage

"Etos siperi elegi"

Tedd

Quote from: Farabi on October 16, 2011, 06:46:57 AM
Haha I got it working  :cheekygreen:
It is simpler than I though, I should just read it better.
Funny how that works :P
No snowflake in an avalanche feels responsible.