DMA interface

[xxxx]

since the 8237 can provide only address A0 to A15,how do i read/write data to address more than FFFF in the IBM PC/XT ?what is the address of the DMA page register?



thanks

[MichaelW]

The PC/XT used an external page register to store the upper four bits of the 20-bit address. AFAICT the page registers for channels 0-3 are at I/O ports 87h, 83h, 81h, and 82h.

[xxxx]

so if i wanted to transfer data from memory location FFFFFH  through channel 2 the code is:

  MOV AX,0FFFFH
  OUT 04H,AL
  MOV AL,AH
  OUT 04H,AL
  MOV AL,0FH
  OUT 81H,AL

correct?
and where can i find the documentation of what port is assigned to what address?

thanks
 

[MichaelW]

From The Undocumented PC, First Edition, Frank van Gilluwe, Addison-Wesley, 1994:

Memory-to-Memory DMA
...
This feature is rarely used because it is slower than an 80386's string move instruction.
...
Memory-to-memory transfers can only be performed with channels 0 and 1. On the original PC, DMA channel 0 was used for DRAM refresh. This makes memory-to-memory transfers much trickier, since the refresh must be disabled while performing the DMA transfer. With long transfers and refresh disabled, the DRAM may loose its contents causing a system crash. In general it's best to avoid memory-to-memory DMA transfers.

To enable memory-to-memory transfers, the Command Register bit 0 is set. The Channel 0 Base Address Register is loaded with the source memory address, and Channel 1's Base Address contains the destination address. Channel 1's Base Word Count Register holds the number of bytes to transfer less 1. The transfer is initiated by setting the DREQ 0 bit high using the Request Register.

The sample code that came with the book performs an I/O-to-memory transfer, because that is how DMA is normally used. I seem to recall seeing a code example that performed a small memory-to-memory transfer somewhere, but I don't recall where.

On an 8088 system, absolute address FFFFFh is at the top of the processor's address space. So AFAIK for a transfer starting at this address bit 5 of the channel's Mode Register would need to be set so the addresses would decrement.

The download version of Ralf Brown's Interrupt List includes a port listing (PORTS.LST) that covers at least some of the DMA-related ports and the bit assignments.

http://www-2.cs.cmu.edu/~ralf/files.html