exception handling

[ninjarider]

im currently disassembling the exception hadler from the bios trying to figure something out.

in 32bit the the error code along with ip cs and some other stuff is pushed on the stack and then passed to the exception hadler throu the idt

does anybody know how the error code, the ip and the cs is passed when in real mode?

[Tedd]

The standard cpu exceptions always work the same way, whether in real or protected mode.
No need for disassembly, full details of what's pushed, and in what order, are in the intel system programming manual (under exceptions :wink). The main thing is that not all exceptions push an error code.

[ninjarider]

ok cool. i was looking at it but i wanted to make sure. the intel book i have is the ia-64/32 book. for some readon there documentation on 16 bit is a little skimpy.

i just want to disassemble it to see what the bios does. it probably doesn't do anything special.

[ninjarider]

another question on the subject.

from my understanding the double fault exception and the system clock interrupt both fall under interrupt 8. how do you tell the difference on which caused the interrupt.

[MichaelW]

AFAIK you would normally do it by checking the IRQ0 in-service bit from the interrupt handler. If the interrupt was caused by the timer hardware then the bit will be set, otherwise the interrupt was caused by a CPU exception. The relevant code should look something like this:

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...
mov al, 0bh   ; read in-service register command
out 20h, al
(delay code may be inserted here)
in al, 20h
test al, 1
jz exception_handler
...


[Tedd]

This is the reason you'd generally use the PIC to remap the irqs to start at int 20h - so they don't overlap on the cpu defined/reserved exceptions. Then the difference is simply whether you get an int 08h, or 28h :wink
Damn legacy defaults ::)

[ninjarider]

have been doing some reading on the apic and tring to find documentation on it and how to program it. finding lots of documentation on it but not any documentation that explains in detail how to program it.

i understand that:
port a for the primary controller is at 20h
port b for the primary controller is at 21h
port a for the seconday controller is at a0h
port b for the secondary controller is at a1h

i've read that the apic 's registers are memeory mapped. i believe it starts at fee0X0??? not sure about that. and how it works.

my main question is, how to program it?

[Tedd]

Linkies! :bg

http://www.osdever.net/tutorials/apicarticle.php
http://www.osdev.org/wiki/APIC

They should put you straight (they also have good links to further info) :wink

[ninjarider]

1) how do i read the is32_apic_base register?

2) concidering the default setting. i write to the initial count register by the follow:
mov ax, 0ffe0h
mov es, ax
mov di, 0380h
mov ax, (low word initial count)
stosw
mov ax, (high word initial count)
stosw

[Tedd]

The apic-base is stored in a MSR, so you have to use the RDMSR instruction:

Code Select Expand

APIC_BASE_MSR    equ 1Bh

mov ecx,APIC_BASE_MSR
rdmsr

;edx:eax => 64-bit msr value (edx = high-dword, eax = low-dword)

(You can probably just ignore edx in this case.)


For reading/writing any of the table values, I would use a single indexed memory access so it's an atomic operation.
Also, remember that if you're in 16-bit mode, you won't be able to access memory that high (16MB limit!) Unless you do something weird through unreal mode.

Code Select Expand

;edx:eax = apic_base

mov edi,eax
mov eax,<initial-count>
mov [edi+0380h],eax
;or you could add to edi first, then write