64 bit regs in 32 bit mode

[vandelay]

Accesses to 32 bit regs are supposed to clear the upper 32 bits of a 64 bit reg, right? e.g. writing EAX would clear the upper 32 bits of RAX. Does this apply to implicit writes too? e.g. if you do a SCAS or MOVS which modifies EDI or ESI, does that clear out the upper 32 bits of RDI or RSI?

[Tedd]

Test it and let us know :wink

[vandelay]

Sure. So when I can expect the 64 bit chip you're mailing me? :p

[P1]

That's like saying, mov ax, 0 then eax the upper 16 bits is cleared.

It does not works that way.

Regards,  P1  :8)

[Ian_B]

Sure. So when I can expect the 64 bit chip you're mailing me? :p

If you only owned and maintained a Ford coupé, would you normally ask a mechanic how to change the turbocharger on a Lamborghini?  ::)

IanB

[manhattan]

According to the documentation the full register is updated.

http://developer.amd.com/documentation.aspx

AMD also has a forum on 64-bit

http://devforums.amd.com/index.php

[PBrennick]

I prefer my Lamborghini with clam sauce, how about you?

Paul

[P1]

According to the documentation the full register is updated.

Op Code utilization is preserved.  IOW, Opcode is the same for mov eax & rax.  That's AMD's way of doing it.   Intel would not have done it that way.

Regards,  P1  :8)

[MazeGen]

Opcodes are not the same. MOV RAX needs REX.W prefix.

[vandelay]

I have to buy a $200k car before I'm allowed to be curious about how a turbo works? Tough crowd.