LEA

[dedndave]

Code Select Expand

        lea     edx,[4*eax+eax]
        lea     ebx,[2*edx+ecx]
        mov     eax,ebx

it would help if you could place unrelated instructions in between..

Code Select Expand

        lea     edx,[4*eax+eax]
        mov     esi,offset SomeData
        lea     ebx,[2*edx+ecx]
        mov     edi,offset SomeOtherData
        mov     eax,ebx

[bomz]

I try LEA NOP MOV ADD. (lea ebx, [ebx])
this method don't still register's for cycle

[qWord]

I try LEA NOP MOV ADD.

you may try to test a useful algorithm!

[bomz]

may be somebody with good or native English write latter to Intel?

[qWord]

may be somebody with good or native English write latter to Intel?

and whats the message for Intel?

[bomz]

how lea work for arithmetic

[qWord]

how lea work for arithmetic

strange question in context to your previous posts - However, you should read Intel's Documentation before asking.

[bomz]

if information about LEA was known I will find it with Google.

[jj2007]

may be somebody with good or native English write letter to Intel?

Hi Bomz,

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:U

[bomz]

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[bomz]

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[redskull]

I haven't looked at the actual code, but anytime you use the same registers for input and output, you'll get a dependency chain. Basically, it can't start the second lea until it knows the output from the first, and can't start the third until its done second, all the way up to 100. With different registers, the value of eax doesn't change, it doesn't have to wait on anything to do any of the lea instructions. But again, that's based on just a cursory look at the results.

-r

[jj2007]

I haven't looked at the actual code, but anytime you use the same registers for input and output, you'll get a dependency chain. Basically, it can't start the second lea until it knows the output from the first

red,

that sounds plausible, and bomz' P4 behaves like that. My Celeron M, in contrast, couln't care less which regs are involved :bg

[redskull]

that sounds plausible, and bomz' P4 behaves like that. My Celeron M, in contrast, couln't care less which regs are involved :bg

Like hutch said, breaking the LEA down into additions and multiplcations is probably what does it.  Per the timings, an M only has a latency of 1 for LEA, but the PIV has a latency of 4.

-r

[bomz]

I haven't looked at the actual code, but anytime you use the same registers for input and output, you'll get a dependency chain. Basically, it can't start the second lea until it knows the output from the first, and can't start the third until its done second, all the way up to 100. With different registers, the value of eax doesn't change, it doesn't have to wait on anything to do any of the lea instructions. But again, that's based on just a cursory look at the results.

-r

and how break this chain?

   lea ebx, [4*EAX+EAX]
   mov edx, ebx
   lea ebx, [2*EDX+ECX]  - 3000

   lea ebx, [4*EAX+EAX]
   mov edx, ebx
   lea ebx, [2*EDX+ECX]
   mov eax, ebx - 10000

This LEA using for matrix?