How to check values of status flags?

[Victor Stout]

Hello. I would like an advice on how to check status flags (CF,PF,AF,ZF,SF and OF) and a simple code example if possible since I'm new to MASM. The reason of this is to get to know the values of data types on a binary level and see how they interact with status flags. Perfect solution to this question would be example that shows steps to be performed on BYTE data type value to affect all (or those that can be affected by manipulation with BYTE) the flags. Thanks.

[donkey]

Normally you push the values onto the stack and pop them into a register.

PUSHFD ; pushes the EFlags
POP eax

you can use BT (Bit Test) to check each individual bit or use boolean operators such as TEST/AND/OR.

A less efficient way is to use the Jcc group of instructions to test for a flag condition and execute code based on the result. For example you can use JC/JNC to test the carry flag or JP/JNP to test the parity flag.

[clive]

or LAHF
Load Flags into AH

http://faydoc.tripod.com/cpu/lahf.htm

[donkey]

Hi clive,

Forgot about LAHF :) Does it include the direction and overflow flags ?

[clive]

Hi clive, Forgot about LAHF :)

Hi Edgar<G>

It's a bit of a dinosaur, tend to use other instructions to recover carry, or extend sign.

With the P6 and beyond you have the conditional instructions SETxxx (ie SETNGE, SETNP, etc)
http://faydoc.tripod.com/cpu/setnge.htm

They are a bit more complicated than perhaps what is sought here, but food for thought.

[jj2007]

Forgot about LAHF :) Does it include the direction and overflow flags ?

AH := SF ZF xx AF xx PF xx CF

It's a lot faster than the pushfd/pop eax combi.

Code Select Expand

Intel(R) Celeron(R) M CPU        420  @ 1.60GHz (SSE3)
841     cycles for 100*pushfd
104     cycles for 100*lahf

Make sure you are not running an Athlon64...!

[KeepingRealBusy]

Forgot about LAHF :) Does it include the direction and overflow flags ?

AH := SF ZF xx AF xx PF xx CF

It's a lot faster than the pushfd/pop eax combi.

Code Select Expand

Intel(R) Celeron(R) M CPU        420  @ 1.60GHz (SSE3)
841     cycles for 100*pushfd
104     cycles for 100*lahf

Make sure you are not running an Athlon64...!

You might want to clarify that to say an "Athlon running in 64 bit mode", works fine in 32 but mode, in 64 bit mode you need to check the status of ecx bit 0 returned by CPUID extended function 8000_0001h to determine if the CPU implementation supports LAHF in 64 bit mode.

Dave.

[Victor Stout]

Thank you.

[dedndave]

Jochen
i have to ask if the test includes a popfd / sahf paired with the pushfd / lahf
seems to me that pushfd and lahf are not the slow ones
it is one thing to examine a flag - it is another thing to explicitly set it

[jj2007]

Jochen
i have to ask if the test includes a popfd / sahf paired with the pushfd / lahf
seems to me that pushfd and lahf are not the slow ones
it is one thing to examine a flag - it is another thing to explicitly set it

See yourself...

Code Select Expand

invoke Sleep, 100
counter_begin LOOP_COUNT, HIGH_PRIORITY_CLASS
REPEAT 100
pushfd
pop eax
ENDM
counter_end
print str$(eax), 9, "cycles for 100*pushfd", 13, 10
invoke Sleep, 100
counter_begin LOOP_COUNT, HIGH_PRIORITY_CLASS
REPEAT 100
lahf
ENDM
counter_end
print str$(eax), 9, "cycles for 100*lahf", 13, 10


[dedndave]

thanks for clarifying, JJ   :bg
the code wasn't attached - so couldn't see it

if you are using 32-bit code, LAHF will get you most of the useful flags
it won't get you the DF, however
it is only when the CPU is in long mode that some CPU's don't support it
i have a prescott - and it does not support LAHF/SAHF in long mode - so AMD isn't the only culprit