CPU identification code

[Antariy]

Hi to all!

I make code for CPU detection, similar to Jochen's (JJ), but my code prints all instruction sets supported by CPU, not only SSE level.
My code support brand name printing, if no CPUID function for brand name - printed family of CPU - PI, PIMMX or PPro. If CPUID unsupported, in this case also works.

Code which makes CPU detection is different from printing code. Detection code fills structure with entryes which have names similar to CPU family or SIMD level. This code can be used differently from printing code.
Printing code is dependent from detection code - and can works with this detection code only, because based on its structure format.

Printing code returns the SIMD level of CPU also - see comments for AxCPUid_Print proc.

Printing code makes something like this:

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Intel(R) Celeron(R) CPU 2.13GHz

Instructions: MMX, SSE1, SSE2, SSE3


If no CPU brand name - will be printed other info about CPU - this is i486, Pentium, Pentium MMX or P6.
If some instruction set are unsupported - then it is not printed, of course :)


I make request to all peoples: test this please, very needed testing on different CPU arch.


Program attached to post contain detection and printing code, also as simple code for show it work.
Printing code have embedded data (CPUs family names, SIMD names etc), therefore total size of all code and data - ~740 bytes. The detection code itself have 228 bytes length.

At this moment supported instructions set to SSE4.2.

I suggest use this CPU detection and printing code in Jochen's and other type testing programs, for clearness, which instructions are supported in each test system.



Alex

[frktons]

This one seems more accurate than the one used for testbed.
This one correctly says that my CPU supports SSE3 code and not SSE4.

The one we use in the testbed says my CPU has SSE4 capabilities, but this is not the case.

Well done Alex  :U

Frank

[redskull]

Nicely done

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Intel(R) Core(TM)2 Duo CPU     E4500  @ 2.20GHz

Instructions: MMX, SSE1, SSE2, SSE3, SSSE3


[hutch--]

Seems OK on my dev Core2 Quad.

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Intel(R) Core(TM)2 Quad CPU    Q9650  @ 3.00GHz

Instructions: MMX, SSE1, SSE2, SSE3, SSSE3, SSE4.1



733 - size of all code and data of AxCPUid filling and printing proc

Press any key to continue ...


I will try it out o.n the i7 later for the SSE4.2 support

[clive]

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Intel(R) Atom(TM) CPU N270   @ 1.60GHz

Instructions: MMX, SSE1, SSE2, SSE3, SSSE3


[dedndave]

i think this machine has a prescott w/htt - lol
i have been playing with a few different ones, recently, as i am on the road
i didn't bring my own machine   :P

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Intel(R) Pentium(R) 4 CPU 2.80GHz

Instructions: MMX, SSE1, SSE2, SSE3

[FORTRANS]

Hi Alex,

   You have the usual problem with a PIII showing
funny characters for a name.  And a couple of others.

Regards,

Steve N.

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PIII with Windows 2000.


☺☺☻♥

Instructions: MMX, SSE1



733 - size of all code and data of AxCPUid filling and printing proc

Press any key to continue ...


Windows XP.

Mobile Intel(R) Celeron(R) processor     600MHz

Instructions: MMX, SSE1, SSE2

Windows 98.

Pentium with MMX Technology

Instructions: MMX


[Rockoon]

AMD Phenom(tm) II X6 1055T Processor

Instructions: MMX, SSE1, SSE2, SSE3


This is missing SSE4a detection, as well as 3DNow and AMD-V .. which brings up an interesting thing to discuss

Instructions like popcnt exist on the newest AMD's and Intel's but are not part of the same "family" of extensions. For AMD its called SSE4a but for Intel its SSE4.2 and some SSE4.1 processors also implement it by itself..

...most important here is that there is a separate CPUID bit that can be tested for the existence of this instruction, so it should probably be classified by itself (much like many programs used to test for the CMOV instructions explicitly)

Other than that, AMD's currently dont implement SSSE3, SSE4.1, or SSE4.2 and Intels do not implement 3DNow, SSE4a, or AMD-V.

[Antariy]

MANY THANKS to ALL!

Steve (FORTRANS), I'll try fix this (funny chars instead name).
I make solution for this, I think that yesterday :), but something is wrong.
I make detection, if no extended functions with brand name, then use family to show, not detailed CPU name. But this is not work, as I see.
Really, I don't debug this app, I make it in one evening, parallel with x64 testing app for Frank, SSSE3 app for Frank too :), and simple app, which I'll attach to post.
I try fix detection code for Pre-PIV CPUs. By the way, instruction set detection works properly.

Rockoon, if you can get me info about checking for all mentioned sets, I will be very grateful to you.
Simplest way to detect set or family - checking for some things, which is started from some family/architecture.


Attached archive contain app, which is probably print number of cores in CPU.
This is typical testing for HTT support - all Prescotts says, what they have HTT, but this is not true sometimes. If cores count is 1 - then this CPU don't support HTT, indeed :)

Please, peoples who have HTT/multicore CPUs - test this prog.



Alex

[Antariy]

Rockoon, CMOV instruction supported not with all of PPro (Intel says this), so I'll make test for PPro (P6) with checking of existence of PAE capabilities, which is PPro familar.



Alex

[dedndave]

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2 - this is needed number
that is correct for this prescott, i believe
i was not aware of prescotts reporting HTT incorrectly
i know some do not support it

[Antariy]

Code Select Expand

2 - this is needed number
that is correct for this prescott, i believe
i was not aware of prescotts reporting HTT incorrectly
i know some do not support it

Dave :)

Of course, I test this code on not-HTT Prescott... Because my CPU is this case :P

Here is results:

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1 - this is needed number


So, my CPU don't support HTT, indeed.

Needed results from CPU with more cores, too.



Alex

[Antariy]

Dave, thanks for test, it make sure how needed test for HTT support. Thanks.



Alex

[Antariy]

i was not aware of prescotts reporting HTT incorrectly

Dave, this is known problem - CPUID EAX=1 reports (bit #4 of last byte of edx) what all 90nm Prescotts support HTT, even if this is not true.



Alex

[Antariy]

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Windows 98.

Pentium with MMX Technology

Instructions: MMX


This is interesing: Pentium not have brand string, and I use this (Pentium with MMX Technology) string for it. And this is work. But the same thing is not work for PIII... Strange. Need to check this. Somebody have PII or PPro to testing?



Alex