Comments on the Core series intel hardware.

[hutch--]

I have the new box part finished and have done just a little playing with a few asm benchmarks on it and the results are interesting. I have an older CPUZ version that recognises the actual processor core(s) as "Katmai" PIII which fits the development of the Core series processors. Only a few basic tests but the much shorter pipeline shows in a couple of test pieces I have tried out and this is in comparison to the PIV I am still using which is a very long pipeline Prescott.

The Prescott PIV is still faster at 3.8 gig than the quad at 3 gig but only on some code, if the code avoids the stalls of a long pipeline its faster, if it bogs down anywhere the Core processor is a fair bit faster and this is with test code that was written for a PIV. I get the impression with a bit more practice and familiarity with the new processor that code written for it will be (a) much closer to PIII code and (b) faster than PIV code when written directly for the Core processor.

What will be worth finding out is if LEA is useful again as it was on all Pentiums before the PIV. On the flip side I remember that a PIII was fussy about different sized data reads and writes and would stall badly if you did a BYTE read after a DWORD write on the same register.

[SteveCurtis]

Hutch,
Could you point me at any resource that shows how to utilise multiple cores? I have a few items (industrial P.C. single board) that use a core duo processors and I would like to be able to boot them from my own code (as you know, I am booting into 16 bit code, setting up PM environment GDT's-IDT's and the rest-- that works!) but would like to know how to treat the multiple processors on the duo arrangement.

Is there a follow-up book along the lines of "Advanced 80386 programming" by Turley? (That was the 'rosetta stone' for me..)

Or are there any resources along the lines of the MASM + related genres that would enlighten suitably?

(BTW I have forgone my 'boot from floppy' dreams just yet. Too many other things to do right away--will get back to that in a month or two.)

Regards,
Steve

[dedndave]

Steve
you might try to find up-to-date documentation on AMD BIOS
as i understand it, multiple cores are enumerated at boot-time, so there is a BIOS table someplace that spells out the cores
most BIOS stuff is down in the BIOS data area at 40:0+, just above the interrupt vector table

[hutch--]

Steve,

I doubt you will have much joy trying to do this stuff in real mode, there is some OS based overhead in setting up milticore operations that probably need protected mode to make it work, just the shared access to memory would probably make that necessary. I would be looking very hard at what the low level hardware does before trying this stuff and you would probably have to write OS level code to do it.

[SteveCurtis]

Steve,

I doubt you will have much joy trying to do this stuff in real mode, there is some OS based overhead in setting up milticore operations that probably need protected mode to make it work, just the shared access to memory would probably make that necessary. I would be looking very hard at what the low level hardware does before trying this stuff and you would probably have to write OS level code to do it.

Thanks Hutch,
Well I expected to be writing PM code to do this anyways. I was just telling you that I had the 16 bit to PM 32 bit jump organised(YAY!:). Basically I boot in to a DOS 16 bit app that calls some assembler, that fixes all the table and interrupt necessities, so I can get myself into PM from DOS (and back if I really want). The issue was more to do with how to handle the multple processor arrangements after that.
Dedndave -- many thanks too I'll take a look at the AMD doco..
Ta Muchly Steve