unreal mode

[MichaelW]

What do you mean by "transfer back and forth from 16 to 32"?

[ninjarider]

in unreal mode dont know what the actual address limit is about 1 meg for the code and only 16-bit is allowed. i can use the 66h overide for it to use 32-bit code but that takes away from any efficiency or performance. pretty much i have to come up with an idt simular to how dos has int 21. wither that or i have to come up with drivers for everything to avoid the int 21h.

hope that makes sense. in short im wanting to be able to have active code reside anywere in the 4 gigs.

[Tedd]

You 'can' have code anywhere in the available memory space, but you need to set up the relevant sector selector for it and load it into CS (far jump) BUT you need to be in protected mode to access the upper part of the segment register selector. In short, :dazzled: This is the main problem with unreal mode. Data can go anywhere too, either with a selector or adding a prefix to use 32-bit instructions (which is annoying and slow to say the least.)

[japheth]

> BUT you need to be in protected mode to access the upper part of the segment register selector

What do you want to tell us with this sentence? What's the "upper part" of a segment register selector?

[Tedd]

In 16-bit mode the segment registers are made to look like they're only 16-bits. The truth is they're still the 48-bit selectors they are in 32-bit mode, but when you do a register load (e.g. "mov cs,10h") in 16-bit, only the bottom 16-bits are loaded (as you'd expect), thus leaving the top 32 bits as they were.. which is most likely not what you want.
It's a bit of a complicated mess to have them working sensibly in 16-bit mode, and even worse to do anything amusing like running code outside of the bottom 16MB, without having setting up and loading a code selector in 32-bit mode first.

Short version: to set the full value (not just the bottom 16-bits) of a segment register you need to do it in 32-bit mode through a valid gdt.

[japheth]

> In 16-bit mode the segment registers are made to lo

I see, you mean the segment register's "descriptor cache"

A "selector" is a 16-bit value whose "upper part" (bits 3-15) addresses an entry in a descriptor table, and bit 2 selects the type of the table (GDT or LDT), so your wording was confusing ... at least for me.

btw., the FASM DOS version runs fast and stable in "32bit" real-mode (as far as the cpu is not from Cyrix), and it has full access to 4 GB both for code and data.