Pointers, etc

[MazeGen]

scale_constant can be 1, 2 or 4

Scale can be 1, 2, 4 or 8.

Didn't know that!  :thumbu

Yeah, that's because Scale is encoded in two bits:

2^0 = 1
2^1 = 2
2^2 = 4
2^3 = 8

base_register can be EBX or EBP
index_register can be ESI, EDI, EAX, ECX or EDX

You can use any combination of any general-purpose registers. The only exception is you can't use ESP as an index (e.g. [EAX+ESP*2] - not encodable), but you can still use ESP as a base (e.g. [ESP+EAX*8])

My bad, I must have been confused with real mode addressing :red

:wink It seems so. In 16-bit addressing, we can use only BP or BX as a base and SI or DI as an index. No scale here.

[Ratch]

To the Ineffable All,
     If you use EBP as a index register, it will cost you an extra byte.  MASM in not smart enough to to reverse the register roles, as is shown in the code below.  Ratch


00000004  8B 14 29       MOV EDX,[EBP+ECX]
00000000  8B 54 0D 00    MOV EDX,[ECX+EBP] ;functionally equavalent to previous instruction
00000007  FF 34 28       PUSH [EBP+EAX]
0000000A  FF 74 05 00    PUSH [EAX+EBP]    ;functionally equavalent to previous instruction

[MazeGen]

I thing it has nothing with a smartness. MASM just compile what you code. I, personally, like such behaviour of an assembler.

[Ratch]

I thing it has nothing with a smartness. MASM just compile what you code. I, personally, like such behaviour of an assembler.

MazeGen,

     Actually, it apprears that coding EBP as a BASE register causes an extra byte to be generated.  MASM appears to ASSUME that the first register is the index register, unless one specifies otherwise.  Is that what you mean when you say that it assembles what you code?  Who says that the first register is an index register?  I think that it should select the shortest instruction if there is an ambiguity about which is what. Perhaps it has something to do with dumbness.  Ratch


00000000  8B 14 29       MOV EDX,[EBP+ECX]   ;assumes ECX is base
00000003  8B 54 0D 00    MOV EDX,[ECX+EBP]   ;assumes EBP is base
00000007  8B 14 29       MOV EDX,[1*EBP+ECX] ;explicit ECX is base
0000000A  8B 14 29       MOV EDX,[ECX+1*EBP] ;explicit ECX is base
0000000D  8B 54 0D 00    MOV EDX,[1*ECX+EBP] ;explicit EBX is base
00000011  8B 54 0D 00    MOV EDX,[EBP+1*ECX] ;explicit EBX is base

[MazeGen]

Sorry, Ratch, I haven't read your post carefully.

The answer is that you should use strict MASM syntax when you expect such encoding:

... If scaling is not used, the first register is the base. ...

        ...
        mov   eax, [edx][ebp]   ; EDX base (first - seg DS)
        mov   eax, [ebp][edx]   ; EBP base (first - seg SS)
        ...

Code Select Expand


00000000  8B 14 29 MOV EDX,[EBP][ECX]   ; EBP is base
00000003  8B 54 0D 00 MOV EDX,[ECX][EBP]   ; ECX is base


[tenkey]

Code Select Expand

8B 4D 00   mov ecx,[ebp]
8B 4D 01   mov ecx,[ebp+1]
8B 0E      mov ecx,[esi]
8B 4E 01   mov ecx,[esi+1]


If you try to encode ecx,[ebp] as 0D, the processor will use the next four bytes as an address.

Code Select Expand

8B 0D 12345678   mov ecx,[ds:12345678H]

[Ratch]

MazeGen,
   The documentation is WRONG!  The first register is truly ASSUMED to be the index, not the base register.  That is easily determined by comparing your two example instructions with the explicit instructions in my example.  Ratch


00000000  8B 14 29       MOV EDX,[EBP+ECX]
00000003  8B 54 0D 00    MOV EDX,[ECX+EBP]
00000007  8B 14 29       MOV EDX,[1*EBP+ECX]
0000000A  8B 14 29       MOV EDX,[ECX+1*EBP]
0000000D  8B 54 0D 00    MOV EDX,[1*ECX+EBP]
00000011  8B 54 0D 00    MOV EDX,[EBP+1*ECX]
00000015  8B 54 0D 00    mov   edx, [ecx][ebp]   ; ECX index, EBP base
00000019  8B 14 29       mov   edx, [ebp][ecx]   ; EBP index, ECX base

[MazeGen]

My apologies, Ratch. I have to be distracted these days or what :(
I use these two (1, 2) tables where it is clear that you are right.

I stop posting to this topic to discontinue the confusion :red

[QvasiModo]

I stop posting to this topic to discontinue the confusion :red

Been there too ;)