I am unable of optimize it more

[theunknownguy]

This is a four-table version that was posted on the old forum by IanB:

Wow. I think I might have processed 16 or 32-byte lines with 4K worth of tables in my footprint.

A lot of efficiencies will likely depend on the size and type of data being handled. For example checking blocks of 512, 4 KB or 32 KB

And the size vs speed trade offs.

Clive got a question, non releated to this subject.

Does WAIT opcode have effect under 32-bit mode?. I am executing it without seen any change on flags, regs, etc.

Thanks (didnt wanted to start a thread for such little question)

[clive]

Does WAIT opcode have effect under 32-bit mode?. I am executing it without seen any change on flags, regs, etc.

It's not something I've really thought about, I suspect it's use is pretty much deprecated now as the co-processor isn't operating autonomously any more but is tightly bound, pipelined and synchronous with the processor.

[dedndave]

it is probably very close to a NOP, as there is nothing connected to the WAIT\ pin

[theunknownguy]

Thanks clive and dedndave, its exactly how i am interpreting this opcode for now... has a NOP  :toothy

[FORTRANS]

Hi,

   When the CPU and FPU were on separate chips (up to 486)
There had to be a way to test if the FPU had finished an
instruction.  WAIT just waited until the FPU finished the current
instruction.  It should do the same thing now, but the only
instructions that probably need it are the ones that store the
FPU state.

Regards,

Steve N.

[theunknownguy]

Hi,

   When the CPU and FPU were on separate chips (up to 486)
There had to be a way to test if the FPU had finished an
instruction.  WAIT just waited until the FPU finished the current
instruction.  It should do the same thing now, but the only
instructions that probably need it are the ones that store the
FPU state.

Regards,

Steve N.

Fuction ftol of an old C++ package:

Code Select Expand

0059897C GameServ._ftol                                                /$  55                                       PUSH EBP
0059897D                                                               |.  8BEC                                     MOV EBP,ESP
0059897F                                                               |.  83C4 F4                                  ADD ESP,-0C
00598982                                                               |.  9B                                       WAIT
00598983                                                               |.  D97D FE                                  FSTCW WORD PTR SS:[EBP-2]
00598986                                                               |.  9B                                       WAIT
00598987                                                               |.  66:8B45 FE                               MOV AX,WORD PTR SS:[EBP-2]
0059898B                                                               |.  80CC 0C                                  OR AH,0C
0059898E                                                               |.  66:8945 FC                               MOV WORD PTR SS:[EBP-4],AX
00598992                                                               |.  D96D FC                                  FLDCW WORD PTR SS:[EBP-4]
00598995                                                               |.  DF7D F4                                  FISTP QWORD PTR SS:[EBP-C]
00598998                                                               |.  D96D FE                                  FLDCW WORD PTR SS:[EBP-2]
0059899B                                                               |.  8B45 F4                                  MOV EAX,[LOCAL.3]                                                 ;  kernel32.7C839AC0
0059899E                                                               |.  8B55 F8                                  MOV EDX,[LOCAL.2]                                                 ;  kernel32.7C817070
005989A1                                                               |.  C9                                       LEAVE
005989A2                                                               \.  C3                                       RETN

How i can possible know if the FPU instruction has ended or not?

I am doing such questions caused i am doing an sandbox for the intel opcodes, but i guess i wont need the WAIT opcode emulation, since the time that delays to emulate each opcode will be enough for the FPU instruction to end...

Thanks

[dioxin]

Originally, the WAIT instruction would make the CPU wait for the FPU to finish to allow synchronisation between the two.
With modern CPUs operations are no longer scheduled one at a time. Instead, a number of instructions are scheduled to take place in parallel as processor resources allow and it no longer made sense to treat FPU operations as a special case when they can be better managed using the same logic that schedules other resources and instructions.

But the WAIT instruction always had another use which was, and still is, to allow exceptions to be raised at appropriate times.
The FPU always raised FP exceptions on the NEXT FP opcode after the cause of the exception. If you need to make sure that no exceptions are pending before continuing then use WAIT to raise the pending exception.


Paul.

[theunknownguy]

But the WAIT instruction always had another use which was, and still is, to allow exceptions to be raised at appropriate times.
The FPU always raised FP exceptions on the NEXT FP opcode after the cause of the exception. If you need to make sure that no exceptions are pending before continuing then use WAIT to raise the pending exception.


Paul.

Wow never knew it, thanks so much. Last question there is a method for finding a FP exception?
Cause you say using WAIT will raise the pending exception, but there is a method to know if i have an FP exception?

[dioxin]

The FNSTSW instruction will store the status register in AX or in memory without causing pending exceptions to be raised. You can then examine the stored value to see which, if any, of the exception bits are set.

Paul.