Cache coherence of a multicore processor?

[houyunqing]

I'm not very familiar with any cache coherence policy... but i want to know
when i write a multi-thread program, can i assume that the L1 caches of the two cores are always coherent? the answer can be just yes/no.
my cpu is Intel Core^TM Duo T5500

[NightWare]

hmm, i don't know what you mean by coherent, but each core has his own L1 cache (appropriate for his own work). and the cores share a L2 cache (where L1 cache load stuff when needed...)

[houyunqing]

I checked out the MESI proctocol on Wikipedia, and according to it, whenever a read is performed, the result you get will always be coherent with the main memory (perhaps in this case the L2 cache) despite some latency for modified shared memory(cache line in I state)

[woonsan]

Actually, we cannot assume that all x86 processors share the Level 2 Cache (Representatively, SMP systems).
In the x86 quad-core architecture, only two cores share the Level 2 Cache.

[houyunqing]

Actually, we cannot assume that all x86 processors share the Level 2 Cache (Representatively, SMP systems).
In the x86 quad-core architecture, only two cores share the Level 2 Cache.

ah... i've never got this clear... IA32/64 is completely different from x86 right? I remember in IA32 all cores share the same L2 cache, and for quad core processors, the L2 cache is 24M, twice that of a duo core processor

[dsouza123]

AMD Phenom X4 have per core L1 and L2 and share the L3.

IA32 is x86, sharing of L2 is different on different CPU generations/families.
Intel also has it's main 64 bit x86 line which includes the Core 2 Quad, Duo etc, they also are fully 32 bit.

The Intel Itanium (and 2) line is 64 bit, EPIC architecture and not x86 (some early ones had hardware emulation of some x86 instructions).
The 24M L2 cache is on one of the Itanium 2 models.

[houyunqing]

Anyway, for  IA32 processors I can always assume that the L1 caches are coherent when read is performed, right? Otherwise what is MESI for?

[woonsan]

Anyway, for  IA32 processors I can always assume that the L1 caches are coherent when read is performed, right? Otherwise what is MESI for?

As you said, MESI is cache coherency protocol. There are many protocols to keep the cache coherency and the MESI is one of them (I think that I heard that the AMD processors use the MOESI protocol -I am not sure).
MESI, M = Modified, E = Exclusive, S = Shared, I = Invalid.
Reference the Intel 64 and IA-32 Architectures Software Developer's Manual for specified information.