How to find Register values for Uart operations

[sprint]

Hello there I am trying to analyze this datasheet and find out the logic behind the working of various registers of UART

I am referring to specific UART - exar 788 and I would like to know how the logic is implemented.I have read the datasheet and I am trying to deduce the following

Read address offset 0x2 (ISR register), the value should be 0x1
Write 0x1 to address offset 0x2
Read address offset 0x2, the value should be 0xC1


Write 0x55 to THR ----   This should send data on the TX pin. 
After a few seconds, can you read the status of the LSR register?  Under normal conditions, the LSR register should be 0x60. 
If it is 0x00, then the data is not being transmitted.


Write 0x40 to LCR ---  This will send a break and force the TX pin low.


http://www.exar.com/interface/uart-and-bridging-solutions/8-bit-vlio-uarts/XR16L788/

Here is the link to the datasheet please let me know as to how this would work

[clive]

The first is a matter of writing to a different register, the ISR is read-only, the two high-order bits are an echo back of the FIFO Enable bit you set writing 0x01 to FCR. This is a classic way to check if hardware is connected. ie have some flip-flops latch bits on one register write, show up in some other bits for a different register.

The second is the state to expect on the status register after the output shift register, or transmit register, and FIFO registers are empty.

[sprint]

Hello Clive thanks for replying but I still have this confusion as to how the two registers could have the same address lines ?? I have attached the image where in it shows the offset if memorymapped would be 0x02 for ISR and also FCR .....And ISR is readonly whereas FCR is write only ....so how is this conflict resolved ...by what logic ???

If I am not wrong this is what I have understood from your explanation.
1) ISR is read-only
2)FCR can be written and its address is same as ISR

so address 0x02 is dual in nature and can be set as readonly/write ------ confused utterly confused :'( ::) ...please let me know thanks

and what causes the value in LSR register to be 0x60 after writing 0x55 to THR ?? how LSR and THR are related ..why 0x60 in this case ???

please explain these clearly ...thanks

[dedndave]

And ISR is readonly whereas FCR is write only

it uses the read/write line as an additional address bit, internally

[sprint]

hello DednDave thanks for replying ...i have read the datasheet but that isn't found....can you please explain about this in more detail ...links,sources,study material of any sort which will help me easily understand these internally wired workings....

And there is no supporting statement in this datasheet ..hard for a newbie like me to comprehend such implicit workings...

thanks again

[dedndave]

this is the supporting documentation...

ISR is read only whereas FCR is write only

that is the only fact you need to sort it out   :P
it tells you how it works, internally

many devices use the same address and data lines, as well as the same address to read and write different registers