I'm porting an atomic API from x86 GNU AS to x86 MASM. Some of the
routines involve mfences. I didn't expect this to be a problem, yet
when I try to use an mfence MASM gives me this error:
"A2085:instruction or register not accepted in current CPU mode". And
this is despite having the code set to the highest CPU mode, .686p (at
least that's the highest that I know of).
What follows is the source file; and then the command line used for
compilation, along with the error message.
P.S. I'm aware that the mfences aren't always necessary, but I'd
rather not do the studying to figure out when and why. I plan to write
the API first, measure client application performance, and then
thinking about whether or not it's worth spending the time optimizing
by learning the finer points of x86 instruction reordering.
========================= MASM Source =========================
TITLE atomic.s
.686p
_TEXT SEGMENT
?atomic_add_32@core@storm@@YAHPCHH@Z PROC
mov ecx, 4[esp]
mov eax, 8[esp]
lock xadd [ecx], eax
add eax, 8[esp]
ret
?atomic_add_32@core@storm@@YAHPCHH@Z ENDP
?atomic_add_32_barrier@core@storm@@YAHPCHH@Z PROC
push ebp
mov ebp, esp
mov eax, 12[esp]
mov ecx, 8[esp]
push eax
push ecx
mfence ; this is line 20
call ?atomic_add_32@core@storm@@YAHPCHH@Z
leave
ret
?atomic_add_32_barrier@core@storm@@YAHPCHH@Z ENDP
_TEXT ENDS
END
================ Command Line ==================
c:\Users\rutski\Documents\projects\storm\src\core\winapi\masm\x86>ml /c atomic.s
Microsoft (R) Macro Assembler Version 9.00.21022.08
Copyright (C) Microsoft Corporation. All rights reserved.
Assembling: atomic.s
atomic.s(20) : error A2085:instruction or register not accepted in current CPU mode
I continued to do some research and found out that .XMM is
also necessary at the top of the file for mfence to be accepted.
Perhaps this is because SSE2 and MFENCE both appeared at about
(if not exactly) the same time.
Problem solved :bg
MFENCE was added as an SSE2 instruction along with LFENCE and CLFLUSH.