in real mode of the microprocessor, the interrupt vector table is present. But, in the protected mode, the interrupt vector table is converted to interrup pointer table... what is the difference and how does the conversion take palce??
thanx in advance.
There is no 'conversion' as such, they are really different things. The OS creates an IPT as part of moving into 32-bit mode, the old 16-bit one is essentially lost.
The 16-bit IVT gives pointers to 16-bit function entry points. The 32-bit IPT stores 32-bit entry points for 32-bit functions, along with a few other bit for protection, operating modes, flags, blah. You'll have to look it up in the intel manuals :P
For real mode the interrupt vector table is just a table of far addresses, where each table entry contains the segment and offset addresses of an interrupt handler. The protected mode equivalent is the interrupt descriptor table (IDT). The OS creates the IDT, and it is not in any way related to the real mode interrupt vector table (so as Tedd stated, there is no conversion). The IDT is essentially a table of interrupt-gate descriptors. This is actually from some old code, but it should give you some idea of what each descriptor contains:
; Structure for gate descriptors
; Extra byte:
; Z:3 Must be 0
; WORD_COUNT:5 Call gates only
; Access rights byte:
; P:1 Present (in memory)
; DPL:2 Descriptor privilege level (0-3)
; Z:1 Must be 0
; TYPE:4 Should be 06h for 286 interrupt gate
GATE_DESCRIPTOR struc
gate_offset_low dw 0
gate_selector dw 0
gate_extra_byte db 0
gate_access_rights db 0
gate_offset_high dw 0
GATE_DESCRIPTOR ends
; Create and initialize IDT
; Offset low w: Offset of handler
; Selector w: CODE_SELECTOR
; Extra b: 0 (default)
; AR b: P = 1, DPL = 00, 0, TYPE = 0006h
; Offset high w: 0 (default)
; Note that the code segment descriptor is recognized as a
; 286 descriptor because the most significant word is 0
idt GATE_DESCRIPTOR <offset Isr00, CODE_SELECTOR, , 86h>, \
<offset Isr01, CODE_SELECTOR, , 86h>, \
<offset Isr02, CODE_SELECTOR, , 86h>, \
<offset Isr03, CODE_SELECTOR, , 86h>, \
<offset Isr04, CODE_SELECTOR, , 86h>, \
<offset Isr05, CODE_SELECTOR, , 86h>, \
<offset Isr06, CODE_SELECTOR, , 86h>, \
<offset Isr07, CODE_SELECTOR, , 86h>
GATE_DESCRIPTOR <offset Isr08, CODE_SELECTOR, , 86h>, \
<offset Isr09, CODE_SELECTOR, , 86h>, \
<offset Isr0A, CODE_SELECTOR, , 86h>, \
<offset Isr0B, CODE_SELECTOR, , 86h>, \
<offset Isr0C, CODE_SELECTOR, , 86h>, \
<offset Isr0D, CODE_SELECTOR, , 86h>, \
<offset Isr0E, CODE_SELECTOR, , 86h>, \
<offset Isr0F, CODE_SELECTOR, , 86h>
GATE_DESCRIPTOR <offset Isr10, CODE_SELECTOR, , 86h>, \
<offset Isr11, CODE_SELECTOR, , 86h>, \
<offset Isr12, CODE_SELECTOR, , 86h>, \
<offset Isr13, CODE_SELECTOR, , 86h>, \
<offset Isr14, CODE_SELECTOR, , 86h>, \
<offset Isr15, CODE_SELECTOR, , 86h>, \
<offset Isr16, CODE_SELECTOR, , 86h>, \
<offset Isr17, CODE_SELECTOR, , 86h>
GATE_DESCRIPTOR <offset Isr18, CODE_SELECTOR, , 86h>, \
<offset Isr19, CODE_SELECTOR, , 86h>, \
<offset Isr1A, CODE_SELECTOR, , 86h>, \
<offset Isr1B, CODE_SELECTOR, , 86h>, \
<offset Isr1C, CODE_SELECTOR, , 86h>, \
<offset Isr1D, CODE_SELECTOR, , 86h>, \
<offset Isr1E, CODE_SELECTOR, , 86h>, \
<offset Isr1F, CODE_SELECTOR, , 86h>
For more information, see the IA-32 Intel Architecture Software Developer's Manual, Volume 3: System Programming Guide, available here:
http://www.intel.com/design/Pentium4/manuals/253668.htm
Micheal and Tedd
thanks, really appreciate the help...