Print Page - SSE4 ?

Title: SSE4 ?
Post by: dsouza123 on March 13, 2006, 01:46:49 AM

The upcoming Merom/Conroe/Woodcrest CPUs have SSE4.
What are the new SSE4 instructions ?
List, descriptions, even the count.

What is needed to use SSE4/SSE3 with ML 6.15 ?

Also curious about SSE3 now that most of the new CPUs
(both INTC and AMD) have the SSE3 instructions.
Found this overview.
http://en.wikipedia.org/wiki/SSE3

Nice instruction FISTTP for truncate (could do an add 0.5 first for round)
without setting rounding modes !

Unfortunately, an equivalent wiki for SSE4 doesn't exist.

(Already searched MASM Forum and the Google results
were without any substance.)

Any informative resouces on SSE# instructions ?
Windows Help, PDF, webpage(s).

Thanks

Title: Re: SSE4 ?
Post by: MazeGen on March 13, 2006, 12:58:48 PM

That's all what I know:

http://board.flatassembler.net/topic.php?t=4756

Title: Re: SSE4 ?
Post by: Mincho Georgiev on March 13, 2006, 01:10:50 PM

SSE4 is a feature that is not yet released /as far as i know/. Last Time, when i heard about it, Intel was intend to use it in the Intel Conroe and Merom.

Here is a nice ref to SSE instruction set:
http://www.cpuid.com/sse.php

and SSE2:
http://www.cpuid.com/sse2.php

Title: Re: SSE4 ?
Post by: dsouza123 on March 13, 2006, 07:35:39 PM

Thanks for the links.

A translated link of a link gave the following list.
Are any of these already in SSE -> SSE3 ?

SSE4:
pabsb
pabsd
pabsw
palignr
phaddd
phaddsw
phaddw
phsubd
phsubsw
phsubw
pmaddubsw
pmulhrsw
pshufb
psignb
psignd
psignw

The trio of new INTC CPUs will replace the Pentium 4/Pentium D, the Pentium M,
and also Yonah Core Duo/Core Solo (which are 32 bit transition CPUs from Pentium M to Merom/Conroe/Woodcrest).

Gains with Conroe et al (Core MicroArchitecture)
Wider (4-way) instruction decoder and more powerful execution units (enhanced integer).
Higher FSB frequency
Improved memory performance
Improved micro-op fusion also new macro-op fusion
EM64T support (ie the 64 bit modes/instruction set)
New multimedia instructions (SSE4)
Shared L2 and transfer between L1 caches. The CPUs are dual core.

Detailed info:
http://www.realworldtech.com/page.cfm?ArticleID=RWT030906143144&p=1

Title: Re: SSE4 ?
Post by: MazeGen on March 14, 2006, 07:17:32 AM

Interesting, it seems none of them is already in some SSE.

I wonder where exactly you got the list?

Title: Re: SSE4 ?
Post by: dsouza123 on March 14, 2006, 05:32:21 PM

Mazegen the SSE4 list is from following the link you posted. :bg

Clicking on the last translated link on the page from the flatassembler link.

Title: Re: SSE4 ?
Post by: MazeGen on March 14, 2006, 05:44:39 PM

:lol Well, I never looked at it.

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General Forums => The Workshop => Topic started by: dsouza123 on March 13, 2006, 01:46:49 AM