Intel' s instruction set manual is misleading:
"The CMOVcc instructions check the state of one or more of the status flags in the
EFLAGS register (CF, OF, PF, SF, and ZF) and perform a move operation if the flags are
in a specified state (or condition). A condition code (cc) is associated with each
instruction to indicate the condition being tested for. If the condition is not satisfied,
a move is not performed and execution continues with the instruction following the
CMOVcc instruction."
NO !!!
Further, on the same page:
Operation
temp ← SRC
IF condition TRUE
CMOVcc—Conditional Move
THEN
DEST ← temp;
FI;
ELSE
IF (OperandSize = 32 and IA-32e mode active)
THEN
DEST[63:32] ← 0;
FI;
FI;
I checked this, and yes, 32 upper bits of the destination register
are zeroed when the condition is not satisfied.
Spread the word because this thing can lead to almost undetectable bugs.
bad documentation - AMD's one is more clear about this:
Quote from: AMD64 Programmers Manual, Volume 3: General-Purpose and System InstructionsIn 64-
bit mode, CMOVcc with a 32-bit operand size will clear the upper 32 bits of the destination register
even if the condition is false.
Right.