This is an undocumented instruction by Intel processors. What I have read, it comes with pentium pro processors. So, I like to know if AMD supports this instruction or not, and they cycles.
QuoteIntel(R) Pentium(R) Dual CPU E2160 @ 1.80GHz (SSE4)
144 cycles, salc REPEAT 100
213 cycles, sbb al,al REPEAT 100
I have added a minimum handler to catch errors if exist.
QuoteAMD Phenom(tm) II X4 955 Processor (SSE3)
93 cycles, salc REPEAT 100
93 cycles, sbb al,al REPEAT 100
Press any key to exit...
It is a 3.2 overclocked to 3.8
I forgot to say, first test this using a debug to see if works. I do not coded a handler to exception.
Intel(R) Atom(TM) CPU N270 @ 1.60GHz (SSE4)
1627 cycles, salc REPEAT 100
399 cycles, sbb al,al REPEAT 100
AMD C-50 Processor (SSE4)
99 cycles, salc REPEAT 100
96 cycles, sbb al,al REPEAT 100
P3:
pre-P4 (SSE1)
197 cycles, salc REPEAT 100
196 cycles, sbb al,al REPEAT 100
On a Prescott P4, salc is a factor 2 faster - 900 instead of 1800 cycles.
See also Collins' secrets page (http://www.rcollins.org/secrets/).
Here is another goodie that is documented but not in the Masm32 opcodes help:
test eax, eax ; 6 bytes
jne @F
mov eax, ecx
@@:
vs
cmovne eax, ecx ; 3 bytes
Unfortunately it is 0.3 cycles slower on the P4 :(
Quote from: mineiro on December 07, 2011, 02:53:20 AM
This is an undocumented instruction by Intel processors. What I have read, it comes with pentium pro processors.
Hi,
It came with the original 8086/88 chip. And it should be
supported by all later x86 style processors.
Regards,
Steve N.
Thanks for the info Sr Fortrans. Strange thing is that the only mention to this opcode/mnemonic in Intel manuals that I have found are:
QuoteThe opcodes D6 and F1 are undefined opcodes reserved by the Intel 64 and IA-32
architectures. These opcodes, even though undefined, do not generate an invalid
opcode exception.
The UD2 instruction is guaranteed to generate an invalid opcode exception.
So, I think is safe use that in some programs.
QuoteIntel(R) Pentium(R) Dual CPU E2160 @ 1.80GHz (SSE4)
197 cycles for 100*jne
128 cycles for 100*cmovne
196 cycles for 100*jne
128 cycles for 100*cmovne
196 cycles for 100*jne
128 cycles for 100*cmovne
196 cycles for 100*jne
128 cycles for 100*cmovne
196 cycles for 100*jne
128 cycles for 100*cmovne
Thank for the link jj2007.
Quote from: GunnerIt is a 3.2 overclocked to 3.8
The number of cycles is not however a function of the processor speed.
AMD Phenom(tm) II X6 1055T Processor (SSE3)
93 cycles, salc REPEAT 100
93 cycles, sbb al,al REPEAT 100AMD Phenom(tm) II X6 1055T Processor (SSE3)
198 cycles for 100*jne
97 cycles for 100*cmovne
201 cycles for 100*jne
97 cycles for 100*cmovne
200 cycles for 100*jne
96 cycles for 100*cmovne
199 cycles for 100*jne
97 cycles for 100*cmovne
198 cycles for 100*jne
97 cycles for 100*cmovne