Hi to all!
I make code for CPU detection, similar to Jochen's (JJ), but my code prints all instruction sets supported by CPU, not only SSE level.
My code support brand name printing, if no CPUID function for brand name - printed family of CPU - PI, PIMMX or PPro. If CPUID unsupported, in this case also works.
Code which makes CPU detection is different from printing code. Detection code fills structure with entryes which have names similar to CPU family or SIMD level. This code can be used differently from printing code.
Printing code is dependent from detection code - and can works with this detection code only, because based on its structure format.
Printing code returns the SIMD level of CPU also - see comments for AxCPUid_Print proc.
Printing code makes something like this:
Intel(R) Celeron(R) CPU 2.13GHz
Instructions: MMX, SSE1, SSE2, SSE3
If no CPU brand name - will be printed other info about CPU - this is i486, Pentium, Pentium MMX or P6.
If some instruction set are unsupported - then it is not printed, of course :)
I make request to all peoples: test this please, very needed testing on different CPU arch.
Program attached to post contain detection and printing code, also as simple code for show it work.
Printing code have embedded data (CPUs family names, SIMD names etc), therefore total size of all code and data - ~740 bytes. The detection code itself have 228 bytes length.
At this moment supported instructions set to SSE4.2.
I suggest use this CPU detection and printing code in Jochen's and other type testing programs, for clearness, which instructions are supported in each test system.
Alex
This one seems more accurate than the one used for testbed.
This one correctly says that my CPU supports SSE3 code and not SSE4.
The one we use in the testbed says my CPU has SSE4 capabilities, but this is not the case.
Well done Alex :U
Frank
Nicely done
Intel(R) Core(TM)2 Duo CPU E4500 @ 2.20GHz
Instructions: MMX, SSE1, SSE2, SSE3, SSSE3
Seems OK on my dev Core2 Quad.
Intel(R) Core(TM)2 Quad CPU Q9650 @ 3.00GHz
Instructions: MMX, SSE1, SSE2, SSE3, SSSE3, SSE4.1
733 - size of all code and data of AxCPUid filling and printing proc
Press any key to continue ...
I will try it out o.n the i7 later for the SSE4.2 support
Intel(R) Atom(TM) CPU N270 @ 1.60GHz
Instructions: MMX, SSE1, SSE2, SSE3, SSSE3
i think this machine has a prescott w/htt - lol
i have been playing with a few different ones, recently, as i am on the road
i didn't bring my own machine :P
Intel(R) Pentium(R) 4 CPU 2.80GHz
Instructions: MMX, SSE1, SSE2, SSE3
Hi Alex,
You have the usual problem with a PIII showing
funny characters for a name. And a couple of others.
Regards,
Steve N.
PIII with Windows 2000.
☺☺☻♥
Instructions: MMX, SSE1
733 - size of all code and data of AxCPUid filling and printing proc
Press any key to continue ...
Windows XP.
Mobile Intel(R) Celeron(R) processor 600MHz
Instructions: MMX, SSE1, SSE2
Windows 98.
Pentium with MMX Technology
Instructions: MMX
AMD Phenom(tm) II X6 1055T Processor
Instructions: MMX, SSE1, SSE2, SSE3
This is missing SSE4a detection, as well as 3DNow and AMD-V .. which brings up an interesting thing to discuss
Instructions like popcnt exist on the newest AMD's and Intel's but are not part of the same "family" of extensions. For AMD its called SSE4a but for Intel its SSE4.2 and some SSE4.1 processors also implement it by itself..
...most important here is that there is a separate CPUID bit that can be tested for the existence of this instruction, so it should probably be classified by itself (much like many programs used to test for the CMOV instructions explicitly)
Other than that, AMD's currently dont implement SSSE3, SSE4.1, or SSE4.2 and Intels do not implement 3DNow, SSE4a, or AMD-V.
MANY THANKS to ALL!
Steve (FORTRANS), I'll try fix this (funny chars instead name).
I make solution for this, I think that yesterday :), but something is wrong.
I make detection, if no extended functions with brand name, then use family to show, not detailed CPU name. But this is not work, as I see.
Really, I don't debug this app, I make it in one evening, parallel with x64 testing app for Frank, SSSE3 app for Frank too :), and simple app, which I'll attach to post.
I try fix detection code for Pre-PIV CPUs. By the way, instruction set detection works properly.
Rockoon, if you can get me info about checking for all mentioned sets, I will be very grateful to you.
Simplest way to detect set or family - checking for some things, which is started from some family/architecture.
Attached archive contain app, which is probably print number of cores in CPU.
This is typical testing for HTT support - all Prescotts says, what they have HTT, but this is not true sometimes. If cores count is 1 - then this CPU don't support HTT, indeed :)
Please, peoples who have HTT/multicore CPUs - test this prog.
Alex
Rockoon, CMOV instruction supported not with all of PPro (Intel says this), so I'll make test for PPro (P6) with checking of existence of PAE capabilities, which is PPro familar.
Alex
2 - this is needed number
that is correct for this prescott, i believe
i was not aware of prescotts reporting HTT incorrectly
i know some do not support it
Quote from: dedndave on September 06, 2010, 10:40:24 PM
2 - this is needed number
that is correct for this prescott, i believe
i was not aware of prescotts reporting HTT incorrectly
i know some do not support it
Dave :)
Of course, I test this code on not-HTT Prescott... Because my CPU is this case :P
Here is results:
1 - this is needed number
So, my CPU don't support HTT, indeed.
Needed results from CPU with more cores, too.
Alex
Dave, thanks for test, it make sure how needed test for HTT support. Thanks.
Alex
Quote from: dedndave on September 06, 2010, 10:40:24 PM
i was not aware of prescotts reporting HTT incorrectly
Dave, this is known problem - CPUID EAX=1 reports (bit #4 of last byte of edx) what all 90nm Prescotts support HTT, even if this is not true.
Alex
Quote from: FORTRANS on September 06, 2010, 12:22:29 PM
Windows 98.
Pentium with MMX Technology
Instructions: MMX
This is interesing: Pentium not have brand string, and I use this (Pentium with MMX Technology) string for it. And this is work. But the same thing is not work for PIII... Strange. Need to check this. Somebody have PII or PPro to testing?
Alex
I'd have to check the Prescott's I have, one supports 64-bit without HTT, and the other HTT but not 64-bit. I'm not aware of them misidentifying, but you can kill HTT in the BIOS.
The Dual PPro's I have need new power supplies, but I think I have another board that should come up. Certainly have some PII systems.
Also all the PPro's I've used have CMOV, but Intel sometimes implies they are optional and other times speaks as if they are always present on PPro and PII architectures.
The code does appear to correctly identify SSSE3 in the Atom, rather than having SSE4 which the other testbed claims, although Intel does claim SSSE4 on one of it's pages, whatever that is. http://ark.intel.com/Product.aspx?id=36331
I got this for my P-3. I wish I had a P-6.
Pentium Pro family (P6)
Instructions: MMX, SSE1
http://en.wikipedia.org/wiki/P6_%28microarchitecture%29
Family : 3=386, 4=486, 5=Pentium, 6=Pentium Pro
I attach "debug" version for testing on FORTRANS CPU PIII. I make temporal "fix" - just checking for having SSE2 - if not - then CPU have not brand name string.
Steve (FORTRANS) test this please on your PIII. Test will print return from CPUID 80000000h - for clearness, what is up on you CPU.
Also I change printing for P6 - PII printed as PII, PIII - as PIII.
Alex
Clive, I saw page about Atom N270, is says what this CPU don't support SSSE3, but SSSE4. How this possible? I use Intel's manual from 2008 year to get CPUID bits, and this must be right, but I not have info about checking for SSS4.
This is specific to Atom - need threat SSSE3 as SSSE4?
Alex
Hi Alex,
Here are the results, PIII Windows 2000. You still
looking for a PII?
Regards,
Steve N.
03020101 Debug message: extended functions count return
Pentium III
Instructions: MMX, SSE1
793 - size of all code and data of AxCPUid filling and printing proc
Press any key to continue ...
Rockoon, you have info which can be reliable used to checking for AMD's extensions?
Sorry, but I have small time for all...
If you don't have detailed info about checking for AMD's extensions, you can get me binary opcodes for specific instruction set?
If CPUID cannot say (or you don't have info) about some sets, this is possible make simple SEH frame, with using all these binary opcodes in ascending order. When #UD will be generated - we would know, what this is not supported :) If catch line where exception are raised - we can found last supported instruction set with easy.
Of course, this is bad method, but if info about sets is not clear or full - this is most reliable checking, I think.
Alex
Quote from: FORTRANS on September 07, 2010, 09:46:34 PM
You still looking for a PII?
Hi,
Steve!
Yes, in this version I add printing for PII also. Now printed not just "PPro family", but short description for each generation.
If you have other P6 generation - test on them please.
Behaviour of CPUID 80000000h on your PIII is strange - Intel not says about that, really :)
In code I check for zero return, or 80000000h (add eax,eax;jz @done), because this is must be right behaviour for not existing extended functions, as far as I know.
Magnum test on PIII also, and his PIII reports about it right in old version of code.
Something implementation specific gives these results maybe.
So, need to check for SSE2 existence - this is most good way :) This way I use in todays' code.
Alex
Quote from: Antariy on September 07, 2010, 09:47:53 PM
Rockoon, you have info which can be reliable used to checking for AMD's extensions?
I have collected the bits that I think matter to userland asm programmers (some of them are for future extensions!)
CPUID(EAX = 1)
ECX
Bit 29 - F16C
Bit 28 - AVX
Bit 25 - AES
Bit 23 - POPCNT
Bit 20 - SSE42
Bit 19 - SSE41
Bit 13 - CMPXCHG16B
Bit 12 - FMA
Bit 9 - SSSE3
Bit 1 - PCLMULQDQ
Bit 0 - SSE3
EDX
Bit 28 - HTT
Bit 26 - SSE2
Bit 25 - SSE
Bit 24 - FXSAVE/FXRSTOR
Bit 23 - MMX
Bit 19 - CLFLUSH
Bit 15 - CMOV
Bit 8 - CMPXCHG8B
Bit 4 - TSC
Bit 0 - x87 FPU
CPUID(EAX = 80000001h)
ECX
Bit 16 - FMA4
Bit 11 - XOP
Bit 6 - SSE4A
Bit 5 - LZCNT
EDX
Bit 31 - 3DNow
Bit 30 - 3DNow+
Bit 37 - RDTSCP
Bit 22 - MMX+
3DNow+ and MMX+ are extensions to each set, respectively. The extended MMX instructions eventually were implemented by Intel in SSE.
Hi,
Results for PII and Windows 98. Your DOS mode stub
seems to be inactive? Anyway it ran in a window.
Regards,
Steve N.
03020101 Debug message: extended functions count return
Pentium II
Instructions: MMX
793 - size of all code and data of AxCPUid filling and printing proc
Press any key to continue ...
Quote from: Rockoon on September 08, 2010, 12:12:05 AM
I have collected the bits that I think matter to userland asm programmers (some of them are for future extensions!)
Thanks,
Rockoon!
"some of them are for future extensions" - this is meant what these bits can be undefined on early AMD architectures?
Alex
Quote from: FORTRANS on September 08, 2010, 03:13:09 PM
Results for PII and Windows 98. Your DOS mode stub
seems to be inactive? Anyway it ran in a window.
Thanks,
Steve!
Yes, I used not working stub with size of 64 bytes. With absence of "Rich garbage" this is make PE header started at 40h offset.
Under DOS running app is not possible - "too big to fit in memory". This is satisfactory for 32bit app under DOS :)
Version posted today - almost yesterdays version, without "Debug message" only.
When I find time, I try implement info which Rockoon gives to me.
Alex
Quote from: Antariy on September 08, 2010, 08:32:47 PM
Quote from: Rockoon on September 08, 2010, 12:12:05 AM
I have collected the bits that I think matter to userland asm programmers (some of them are for future extensions!)
Thanks, Rockoon!
"some of them are for future extensions" - this is meant what these bits can be undefined on early AMD architectures?
Alex
I believe that by Intel/AMD definition, all "undefined" and "reserved" bits must be 0 on return from CPUID. That is, they never report true until the usage is defined. The instruction would be almost pointless otherwise.
CPUID leaf 80000000h returns the largest supported extended leaf.
To ID the Pentium 1/Pro/2/3's, use the Processor Signature from leaf 00000001h EAX register.
The Intel document 241618.PDF has quite a few errors in the Signature table.
I have corrected most, if not all, of these errors in the Signature table pic...
http://www.4shared.com/file/WHXNrzwq/Signature.html
If you read the footnotes, it points you to the individual update PDF's for the Pentium 1/Pro/2/3 Family/Models.
This is primarily where I got the correct info, along with sites like cpuworld, etc, that have partial CPUID dumps.
You may also want the Brand Index and L2 Cache type to identify specific chips.
The Family and Model values are combined in the low-order byte of the 00000001h leaf EAX Signature (AL).
For later 486's that support CPUID, the Family bits are 0100.
For the Pentium I's, the Family bits are 0101.
All the Pentium Pro/2/3's are in Family 0110 - use the low 4 bits (Model) to sort them out.
Update: As I recall, all Intel CPU's prior to family 6, model 0Bh do not support Brand String.
All Intel CPU's from family 6, model 0Bh and up do support Brand String.
I think nearly all AMD chips do support Brand String.
The AMD CPUID document is...
http://support.amd.com/us/Processor_TechDocs/25481.pdf
Quote from: Rockoon on September 08, 2010, 10:56:27 PM
I believe that by Intel/AMD definition, all "undefined" and "reserved" bits must be 0 on return from CPUID. That is, they never report true until the usage is defined. The instruction would be almost pointless otherwise.
Yes, this is *must* be right behaviour. But, for example for Steve's PIII, extended function 80000000h returns 03020101h, not zero as must. This is strange and funny. Magnum's PIII return zero as needed, because on his machine old code identify his CPU right.
Alex
Quote from: dedndave on September 09, 2010, 01:14:26 PM
CPUID leaf 80000000h returns the largest supported extended leaf.
To ID the Pentium 1/Pro/2/3's, use the Processor Signature from leaf 00000001h EAX register.
The Intel document 241618.PDF has quite a few errors in the Signature table.
I have corrected most, if not all, of these errors in the Signature table pic...
http://www.4shared.com/file/WHXNrzwq/Signature.html
If you read the footnotes, it points you to the individual update PDF's for the Pentium 1/Pro/2/3 Family/Models.
This is primarily where I got the correct info, along with sites like cpuworld, etc, that have partial CPUID dumps.
You may also want the Brand Index and L2 Cache type to identify specific chips.
The Family and Model values are combined in the low-order byte of the 00000001h leaf EAX Signature (AL).
For later 486's that support CPUID, the Family bits are 0100.
For the Pentium I's, the Family bits are 0101.
All the Pentium Pro/2/3's are in Family 0110 - use the low 4 bits (Model) to sort them out.
Update: As I recall, all Intel CPU's prior to family 6, model 0Bh do not support Brand String.
All Intel CPU's from family 6, model 0Bh and up do support Brand String.
I think nearly all AMD chips do support Brand String.
The AMD CPUID document is...
http://support.amd.com/us/Processor_TechDocs/25481.pdf
Thanks
Dave, I know what does CPUID EAX=80000000h :P
I make this code not for all possible CPUs, this code just for using in us testbeds. So, it don't show many things, and not support many CPUs (Transmeta, VIA etc). This is simple code, I don't trying make something all-embracing.
In short words, all pre-PIV CPUs of Intel don't have brand name string. Maybe last revisions of PIII (crutches like 2.5GHz upclock) have brand-name, because released after first PIV.
I think, I used simplest and reliable method of detection for Intel's CPUs generation and extensions.
If I implement AMDs bits which Rockoon gives to me, then I'll based checking for AMD with CPUID EAX=0 and return ECX="DMAc" :P
Dave, thanks for info and links, I downloaded AMDs PDF.
Alex
On page: "http://software.intel.com/en-us/articles/multi-core-detect/" I found this quote for
Dave, because he is not believe to me, what Prescott may be not HTT even if HTT bit is set. Since Dave cannot see my system (Dave, come to me :), I give this link and quote.
Quote
Logical Processors per Package (CPUID.1.EBX[23:16]) — Indicates the maximum number of logical processors in a physical package. This represents the hardware capability of the processor as manufactured, and does not necessarily equate to the number of logical processors enabled by the platform bios or operating system.
Method which I used in cores.zip and suggest to Gunther for checking for real HTT support is reliable. These bits shows number of logical CPUs (if CPU have 2 physical cores - this is equal to 2 logical, at least).
So, I only shift by 16 bits, and mask bh. In ebx (bl) - count of cores. If HTT (#28 of EDX) bit is set, but cores count is 1 - then CPU don't support HTT. Because BIOS is not have meaning on results of CPUID EAX=1 EBX[23:16] (read quote or link).
Alex
Edit: wrong information, sorry.
SRN
Quote from: FORTRANS on September 10, 2010, 12:40:20 PM
Edit: wrong information, sorry.
SRN
:eek
I not saw your initial post,
Steve! :)
Alex
Hi,
It was about testing the CPUID instruction to see if extended
functions existed on older processors like the PII and PIII. And
it was wrong when I double checked the Intel document. So,
rather than trying to explain or correct it, I just edited it away.
Regards,
Steve
Quote from: FORTRANS on September 10, 2010, 10:01:06 PM
Hi,
It was about testing the CPUID instruction to see if extended
functions existed on older processors like the PII and PIII. And
it was wrong when I double checked the Intel document. So,
rather than trying to explain or correct it, I just edited it away.
Regards,
Steve
No problem,
Steve.
In manual, which I have, Intel suggest test for 80000000h - if returned this value, then no brand string. But I'm using more reliable - add eax,eax (to drop higher bit and leave only little bits). I expect, what CPUID must return 0 or 80000000h if CPU have not extended functions, but Intel make some mess :) So, I checked for SSE2, too.
Thanks for testing and help - maybe not many PIII CPUs have that behaviour - so, your test is VERY helpful.
Alex
Dave (dedndave), thanks, I downloaded Signature.zip also.
Alex