Segment Arithmetic Problem:->
Here is how the
processor combines a 16-bit segment and a 16-bit offset to form a 20-bit linear
address. In effect, the segment selects a 64K region of memory, and the offset
selects the byte within that region. Here's how it works:
1. The processor shifts the segment address to the left by four binary places,
producing a 20-bit address ending in four zeros. This operation has the effect
of multiplying the segment address by 16.
The processor shifts the segment address to left by four binary places,producing a 20-bit address ending in four zeros.
My question is that how a 16 bit address is converted to a 20 bit address and thus shifting results to (1) or (2)??
I have taken an example, that suppose our segment address is 5 in 16 bit binary it is 0000000000000101,and when we shift it four places
to left (5<<4),it becomes (1)00000000000001010000 this or (2)0000000001010000 this??.
According to my shifting (2) result will be there but if I am wrong then please
correct me.
I have shifted like this :->
1:-> 0000000000001010
2:-> 0000000000010100
3:-> 0000000000101000
4:-> 0000000001010000
QuoteNow I am not getting that how this becomes a 20 bit address??
Does the processor itself adds additional 4 bits to the address,in my case like this 00000000000001010000,before shifting the address??
How r u dedndave? :bg
Thanks in advance.
EnFeR RoI.
I moved this because the 20-bit address generation mechanism is for real mode only.
The segment address selects a region that can be up to 64KB. To create a 20-bit absolute address the processor effectively shifts the 16-bit segment address left by 4 bits, stores it in a 20-bit result, and then adds in the 16-bit offset address. To use a real example, the BIOS data area is stored at segment address 40h, and within that area the number of timer ticks since midnight is stored at offset 6Ch.
0000 0000 0100 0000 = 40h
0000 0000 0110 1100 = 6Ch
0000 0000 0100 0000 0000 = 400h
0000 0000 0000 0110 1100 = 6Ch
-------------------------------
0000 0000 0100 0110 1100 = 46Ch
in truth, the processor probably doesn't shift anything
it is simply wired so that segment address lines are treated with 20 bits, the lower 4 always being 0
the reason i make that distinction is that shifting would require clock cycles :P
a picture is worth 1024 words....
(http://www.arl.wustl.edu/~lockwood/class/ece291/lecture/seg-off.gif)
Thanks for the reply!!!
Thanks in advance.
EnFeR RoI. :bg
Quote from: MichaelW on January 19, 2010, 05:08:36 PM
I moved this because the 20-bit address generation mechanism is for real mode only.
The segment address selects a region that can be up to 64KB. To create a 20-bit absolute address the processor effectively shifts the 16-bit segment address left by 4 bits, stores it in a 20-bit result, and then adds in the 16-bit offset address. To use a real example, the BIOS data area is stored at segment address 40h, and within that area the number of timer ticks since midnight is stored at offset 6Ch.
0000 0000 0100 0000 = 40h
0000 0000 0110 1100 = 6Ch
0000 0000 0100 0000 0000 = 400h
0000 0000 0000 0110 1100 = 6Ch
-------------------------------
0000 0000 0100 0110 1100 = 46Ch
Thanks sir for the reply, now i understand the concept....
Thanks in advance.
EnFeR RoI.
Quote
To create a 20-bit absolute address the processor effectively shifts the 16-bit segment address left by 4 bits, stores it in a 20-bit result
My question is that how the address is shifted??,as I have given the example in my post (the example of address 5).
Does the processor is predefined to add additional four bits like this:->00000000000001010000 (at the end of the 16 bit number after shifting it to four places left)?
Or simple shifts the number like this:->0000000001010000 (and then puts additional four zeros in the beginning to make it a 20 bit number like this 00000000000001010000 ).
Thanks in advance.
EnFeR RoI.
put 4 zero bits at the end (low order end) of the segment value
put 4 zero bits ar the beginning (high order end) of the offset value
then, add the two values together
16-bit code can address 1 Mb of address space - this requires 20 bits
at any given time however, you can only address 64 Kb of address space with 16-bit values
the segment value defines the base of the 64 Kb segment as a "window" into the 1 Mb of memory
a good example of this is the video buffer
for most text modes, the buffer is at B8000h (20 bits) in the 1 Mb address space
a good way to access the video buffer is to put a segment value of B800h (16 bits) into the ES register
then, an address of ES:0000 is the base of the video buffer
without changing the ES segment register, you can address 64 Kb of address space, starting at B8000h
on a simplified x86 model, you have 4 segment registers
CS code segment
DS data segment
ES extra segment
SS stack segment
the 4 segment registers may address different 64 Kb areas of the 1 Mb address space
QuoteMy question is that how the address is shifted??
If I understand your question, the answer would require detail knowledge of the inner workings of the processor, knowledge that only the designers of the processor would be likely to have. This is why my description included the word "effectively", meaning that the end result is the same as if the processor had stored the segment address in a 20-bit register, shifted it left by 4 bits, and then added the offset address. I think the actual process is likely to be closer to what Dave described.
Quote
To create a 20-bit absolute address the processor effectively shifts the 16-bit segment address left by 4 bits, stores it in a 20-bit result
My question is that how the address is shifted??,as I have given the example in my post (the example of address 5).
Does the processor is predefined to add additional four bits like this:->00000000000001010000 (at the end of the 16 bit number after shifting it to four places left)?
Or simple shifts the number like this:->0000000001010000 (and then puts additional four zeros in the beginning to make it a 20 bit number like this 00000000000001010000 ).
Thanks in advance.
EnFeR RoI :'(
I guess it depends on the size of the register/memory area you are storing it in.... if you are shfting a 16 bit register you will still have a 16 bit register not a 20 bit register
Hi,
In the original 8086/88 processors, I think it was hard-
wired as in the picture dedndave posted. The bits in the
offset are taken from memory or a register and latched,
then the segment bits are added with those and placed
on the address lines with no "internal register" being
used. So the four "extra bits" needed for each don't
really exist per say. The "shift" of the segment is done
with the Bus Interface Unit's hardware.
In newer processors, you have some indirection for
memory management in protected modes, so some
internal register should exist. However, as a user, you
have no access to it other than feeding it an offset
and segment in real or virtual 86 modes.
BITS
O S A
F E D
F G D
S M R
E E E
T N S
T S
0 - - - - -> AD0
1 - - - - -> AD1
2 - - - - -> AD2
3 - - - - -> AD3
4 + 0 - - > AD4
5 + 1 - - > AD5
6 + 2 - - > AD6
7 + 3 - - > AD7
...
13 + 9 - - > AD13
14 + 10 - - > AD14
15 + 11 - - > AD15
12 - - > A16
13 - - > A17
14 - - > A18
15 - - > A19
Regards,
Steve N.
Hello everyone, I am not getting you man,can you please explain in the form of my example as I took the address 5 as the segment address.
Now with the help of this example can you tell me what really happens..
Segment address=5;
Offset=take your own;
Now Segment:Offset=Linear address?
Now can you tell that what will be the linear address.
I think I was a bit rude ::) But never mind.
Thanks in advance.
EnFeR RoI.
Now its your post
Quote
The segment address selects a region that can be up to 64KB. To create a 20-bit absolute address the processor effectively shifts the 16-bit segment address left by 4 bits, stores it in a 20-bit result, and then adds in the 16-bit offset address. To use a real example, the BIOS data area is stored at segment address 40h, and within that area the number of timer ticks since midnight is stored at offset 6Ch.
Code:
0000 0000 0100 0000 = 40h
0000 0000 0110 1100 = 6Ch
0000 0000 0100 0000 0000 = 400h
0000 0000 0000 0110 1100 = 6Ch
-------------------------------
0000 0000 0100 0110 1100 = 46Ch
And why it is not like this 0000 0000 0100 0000 0000 - 40h(additional 0's in last.)
0000 0000 0110 1100 0000 - 6C0h(additional 0's in last)
----------------------------------
0000 0000 1010 1100 0000-AC0
And this 0000 0000 0000 0100 0000- 40h (additional 0's in begn.)
0000 0000 0000 0110 1100- 6Ch(additional 0's in begn.)
-------------------------------------
0000 0000 0000 1010 1100-ACh
Can you please explain that how it is recognized that when to add the additional zeros in beginning and in the end.
And please also tell that IS 6Ch=108 in decimal or not?("h" is for hexa-decimal I think).
If not then what C stands for?In context to this example.
Thanks in advance.
EnFeR RoI.
Take your 16 bit segment address, add a '0' to the end (makes it 20 bit) then add the offset
segment=5 -> linear=50h
segment=40h -> linear=400h
segment=0a000h -> linear = 0a0000h
i think Michael had a good example, so let's stay with that one
what may be confusing you is all the shifting and adding 0's
let's try it without all that.....
0000 0000 0100 0000 = 40h segment
0000 0000 0110 1100 = 6Ch offset
0000 0000 0100 0000 = 40h segment
0000 0000 0110 1100 = 6Ch offset
------------------------
0000 0000 0100 0110 1100 = 46Ch linear address
QuoteMy question is that how the address is shifted?
Either I don't understand your question, or you are asking for information that I doubt anyone here can provide. If you want to know exactly how the processor works internally, you would need to ask the designers. Programmers work with a programming model of the processor, and since this particular feature is not directly programmable there is no reason to include the details of it in the model. Basically, the programming model provides only the information that the programmer needs, and in this case that is the end result of the address translation. This description is from a recent version of the Intel IA-32 Software Developer's Manual, Volume 3 System Programming Guide, under 16.1.1 Address Translation in Real-Address Mode:
Quote
In real-address mode, the processor does not interpret segment selectors as indexes into a descriptor table; instead, it uses them directly to form linear addresses as the 8086 processor does. It shifts the segment selector left by 4 bits to form a 20-bit base address (see Figure 16-1). The offset into a segment is added to the base address to create a linear address that maps directly to the physical address space.
And Figure 16-1 shows the operations as if they were being done in 20-bit registers. So here is a diagram of your segment address of 5 and an offset address of 17, both copied to 20-bit registers and processed from there:
Take your 16-bit segment address:
0000 0000 0000 0101
Copy it to a 20-bit register:
0000 0000 0000 0000 0101
Shift it left by 4 bits:
0000 0000 0000 0101 0000
Take a 16-bit offset address (of 17):
0000 0000 0001 0001
Copy it to a 20-bit register:
0000 0000 0000 0001 0001
And add the two together:
0000 0000 0000 0101 0000
0000 0000 0000 0001 0001
------------------------
0000 0000 0000 0110 0001
And here is a map of what the memory would look like, starting at segment address 0 offset address 0, and extending to segment address 6 offset address 0Fh, with the segment addresses in the leftmost column and all the values in hex, and with the value FFh shored in the addressed byte:
0000 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
0001 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
0002 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
0003 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
0004 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
0005 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
0006 00 FF 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
finally i got the answer as explained by you MichaelW Sir.... :U
Thanks for cooperating me!!
EnFeR RoI.
C, in this case, stands for a 12.
6Ch = 6 12 = 0110 (6) 1100 (12) = 0110 1100 (binary) = 2^2+ 2^3 + 2^5 + 2^6 = 108 in decimal.
I hope this clarifies a bit. If not, I will try and make it more clear.