I know this is not new (http://www.masm32.com/board/index.php?topic=6595.0). Here is a little routine intended as a convenient way to tell each other which CPU we used to speed test an algo.
Usage:
call ShowCPU
Output:
Pentium 4 Prescott (2005+), MMX, SSE3
Full source with some references attached, for improvement. The usage of CPUID by various manufacturers seems a messy and sometimes hilarious story - see bottom of the source.
[attachment deleted by admin]
Quote from: AMD XP 4400+ dual-core x64
Short version:
Pentium 4 (?), MMX, SSE3
Full version:
CPU family 15, model 11, Pentium 4 (?), MMX, SSE3
Step 1
Model 11
Family 15
Type 0
Ext model 6
Ext family 0
Manufacturer AuthenticAMD
Quote from: Pentium D 940 dual-core x64Short version:
Pentium 4 (?), MMX, SSE3
Full version:
CPU family 15, model 6, Pentium 4 (?), MMX, SSE3
Step 4
Model 6
Family 15
Type 0
Ext model 0
Ext family 0
Manufacturer GenuineIntel
Thanx. I have added these two, but I see it's getting more and more messy. Don't be surprised if you see an "AMD Pentium" :wink
There is a list at sandpile (http://www.sandpile.org/ia32/cpuid.htm), but it is not so organised. One would really need a database to do it properly...
The executable can be run from the commandline as cpuid full or cpuid short. However, the main purpose is to include it into algos using TIMER.ASM, so that those who post timings don't have to bother about adding their CPU info.
EDIT: Attached an example with three applications:
1. CpuID shows how \masm32\include\CpuID.INC can be included in a simple program
2. StrCopy shows how the CPU info is displayed in a testbed
3. StrCopy also includes an algo (MbCopy) where the processor type is being used to decide whether the source or the destination data of a string copy should be pre-aligned. On an Intel Core, source alignment is over 10% faster; the opposite is true for a Pentium 4. I have not yet had a chance to test other CPUs - grateful for postings.
(note that \masm32\include\CpuID.INC is a hard-coded path)
EDIT(2): Updated with brand string, as suggested by evlncrn8
[attachment deleted by admin]
to get the name, why not use the 0x8000002 cpuid ? :) (check using the 0x80000000 cpuid to see if its supported, if so, take the name from 0x80000002->0x80000004... problem solved
Quote from: evlncrn8 on February 12, 2009, 10:59:16 AM
to get the name, why not use the 0x8000002 cpuid ? :) (check using the 0x80000000 cpuid to see if its supported, if so, take the name from 0x80000002->0x80000004... problem solved
Thanks, I had not yet discovered that one. Great feature - any idea since when it is supported for AMD's? Intel introduced it with the Pentium 4, apparently.
think its been in since pentium 4 days, so i think anything within the last 6-8 years (possibly more) should do the job, if it returns nothing, just use your old code... 0x8000000 cpuid = amount of levels supported
if this is = 0 or < 80000004 then go with the old code, otherwise work from this new stuff :)
I am adding mine as it has not been listed yet and may be a help.
Quote
Short version:
Itanium 2 (2002+), MMX, SSE2
Full version:
CPU family 15, model 1, Itanium 2 (2002+), MMX, SSE2
Step 3
Model 1
Family 15
Type 0
Ext model 0
Ext family 0
Manufacturer GenuineIntel
Paul
Both returns look correct, as far as they go. I'm not sure exactly what the 2000+ means, but I'm fairly certain that the CPU was fabricated not later than 1999.
Intel P3 (2000+), MMX, SSE1
Your CPU:
CPU family 6, model 7
Step 3
Model 7
Family 6
Type 0
Ext model 0
Ext family 0
Manufacturer GenuineIntel
Description Intel P3 (2000+), MMX, SSE1
QuoteHere is a little routine intended as a convenient way to tell each other which CPU we used to speed test an algo.
What about not using CPUID? I mean it could save you a lot of time if you just use Registry to extract info.
Nice and small:
BasicInfo proc uses esi edi ebx
LOCAL hKey,nbr,rtype,freq,feat1,feat2
local procnamestr[64]:byte
LOCAL sysinfo:SYSTEM_INFO
LOCAL osver:OSVERSIONINFO
local featbuff[128]:byte
mov osver.dwOSVersionInfoSize,sizeof osver
invoke GetVersionEx,addr osver
invoke GetSystemInfo,addr sysinfo
invoke printf,T('OS : Windows v%u.%u.%u %s',CRLF),osver.dwMajorVersion,osver.dwMinorVersion,osver.dwBuildNumber,addr osver.szCSDVersion
invoke printf,T('Processor : (%ux) '),sysinfo.dwNumberOfProcessors
invoke RegOpenKeyEx,HKEY_LOCAL_MACHINE,T("HARDWARE\DESCRIPTION\System\CentralProcessor\0"),0,KEY_ENUMERATE_SUB_KEYS or KEY_READ or KEY_QUERY_VALUE,addr hKey
mov nbr,sizeof procnamestr
mov rtype,REG_SZ
invoke RegQueryValueEx,hKey,T('ProcessorNameString'),0,addr rtype,addr procnamestr,addr nbr
mov nbr,sizeof DWORD
mov rtype,REG_DWORD
invoke RegQueryValueEx,hKey,T('~MHz'),0,addr rtype,addr freq,addr nbr
invoke RegCloseKey,hKey
invoke strcat,addr procnamestr,T(' ~ ')
invoke strlen,addr procnamestr
invoke _itoa,freq,addr procnamestr[eax],10
invoke strcat,addr procnamestr,T(' MHz',CRLF)
invoke printf,addr procnamestr
invoke strcpy,addr featbuff,T('[SSE : ][SSE2: ]')
mov eax,1
cpuid
lea ebx,featbuff
bt edx,25
; SET GLOBALS HERE:
; setc byte ptr YesNoCanDoSSE
sbb eax,eax
and eax,'SEY '-' ON '
add eax,' ON '
mov dword ptr featbuff[6],eax
bt edx,26
; setc byte ptr YesNoCanDoSSE2
sbb eax,eax
and eax,'SEY '-' ON '
add eax,' ON '
mov dword ptr featbuff[17],eax
invoke printf,T('Features : %s'),addr featbuff
invoke puts,T(0)
ret
BasicInfo endpmine:
OS : Windows v5.1.2600 Service Pack 3
Processor : (1x) AMD Opteron(tm) Processor 148 ~ 2210 MHz
Features : [SSE : YES][SSE2: YES]yours:
Your CPU:
CPU family 15, model 7
Step 1
Model 7
Family 15
Type 0
Ext model 2
Ext family 0
Manufacturer AuthenticAMD
Description AMD AMD (?), MMX, SSE3
Quote from: MichaelW on February 13, 2009, 07:14:37 PM
Both returns look correct, as far as they go. I'm not sure exactly what the 2000+ means, but I'm fairly certain that the CPU was fabricated not later than 1999.
the 2000+ is the speed in mhz that the chip is reporting :)
Quotethe 2000+ is the speed in mhz that the chip is reporting :)
I wish...it's clocked at 500MHz.
Here is the source of the "2000+" etc bits:
CPUID Family codes (http://www.pagetable.com/?p=18)
* 486 (1989): family 4
* Pentium (1993): family 5
* Pentium Pro (1995): family 6, models 0 and 1
* Pentium 2 (1997): family 6, models 3, 5 and 6
* Pentium 3 (2000): family 6, models 7, 8, 10, 11
* Itanium (2001): family 7
* Pentium 4 (2000): family 15/0
* Itanium 2 (2002): family 15/1 and 15/2
* Pentium M (2003): family 6, models 9 and 13
* Core (2006): family 6, model 14
* Core 2 (2006): family 6, model 15 @
I have updated the algo, see above, it now has a short form:
Intel(R) Celeron(R) M CPU 420 @ 1.60GHz (SSE3)
The SSE level is in the global variable CpuSSE.
Quote from: PBrennick on February 13, 2009, 06:25:16 PM
I am adding mine as it has not been listed yet and may be a help.
Thanks, Paul, and welcome back to the forum :thumbu
Quote from: drizz on February 13, 2009, 07:23:48 PM
QuoteHere is a little routine intended as a convenient way to tell each other which CPU we used to speed test an algo.
What about not using CPUID? I mean it could save you a lot of time if you just use Registry to extract info.
Nice and small:
You are pulling my leg, drizz. But you are right, it could be a lot shorter. What really matters is the brand string
mov esi, 80000002h
mov edi, offset CpuBrand
.Repeat
mov eax, esi
db 0Fh, 0A2h ; cpuid 80000002h-80000004h
stosd
mov eax, ebx
stosd
mov eax, ecx
stosd
mov eax, edx
stosd
inc esi
.Until esi==80000005h
... and the SSE level in case you need to decide which branch to take in an algo:
push 1
pop eax
db 0Fh, 0A2h ; cpuid 1
mov CpuFlags, edx
mov CpuExFlags, ecx
and CpuMMX, 0
and CpuSSE, 0
...
mov edx, CpuFlags
bt edx, 25
jnc @F
inc CpuSSE ; edx bit 25, SSE1
@@:
bt edx, 26 ; edx bit 26, SSE2
jnc @F
inc CpuSSE
@@:
mov ecx, CpuExFlags
bt ecx, 0 ; ecx bit 0, SSE3
jnc @F
inc CpuSSE
@@:
bt ecx, 9 ; ecx bit 9, SSE4
jnc @F
inc CpuSSE
@@:
Hi jj2207:
Nice program!
Is rhey any place we can get instructions spec on CPUID.
I am having alsorts of problems wirh it in windbg.
Regards herge
The Intel and AMD manuals contain all the info for CPUID.
There is something simple to use,a dos window
Quote
NUMBER_OF_PROCESSORS=1
PROCESSOR_ARCHITECTURE=x86
PROCESSOR_IDENTIFIER=x86 Family 15 Model 4 Stepping 1, GenuineIntel
PROCESSOR_LEVEL=15
PROCESSOR_REVISION=0401
ProgramFiles=C:\Program Files
direct access can be made by
GetEnvironmentStringsIt is made for each program by the system;speed and easy
registry can also give that,but it is slower
CPUID answer to many questions,with help of the manuals (intel amd) but need some headers define.
Nice gadget jj.
C:\Temp>cpuid short
Intel(R) Pentium(R) D CPU 2.80GHz (SSE3)
C:\Temp>cpuid full
This is your CPU:
Model 6
Family 15
Step 4
Manufacturer GenuineIntel
Description Intel Pentium dual-core x64, SSE3
Brand name Intel(R) Pentium(R) D CPU 2.80GHz
C:\Temp>
Quote from: ToutEnMasm on March 23, 2009, 01:39:16 PM
There is something simple to use,a dos window
Quote
NUMBER_OF_PROCESSORS=1
PROCESSOR_ARCHITECTURE=x86
PROCESSOR_IDENTIFIER=x86 Family 15 Model 4 Stepping 1, GenuineIntel
PROCESSOR_LEVEL=15
PROCESSOR_REVISION=0401
ProgramFiles=C:\Program Files
Very simple, but how can I tell my code if the CPU supports SSE2, using this info?
And how do I get the brand name, e.g. " Intel(R) Pentium(R) 4 CPU 3.40GHz (SSE3)"?
I was not saying that you can have all the needed informations as this.
it's a very interesting way to have informations,that all.
Quote
direct access can be made by GetEnvironmentStrings
It is made for each program by the system;speed and easy
registry can also give that,but it is slower
CPUID answer to many questions,with help of the manuals (intel amd) but need some headers define.
There is one,in particular,that isn't shown by your prog.
Quote
NUMBER_OF_PROCESSORS=1
Just an idea, but how about setting up a SEH chain and actually testing an instruction from each extension? MMX, SSE, etc.
While I _do_ think this is a great approach in this discussion be warned that if you code such a handler you will be a prime candidate for generating false positives as this is a popular method used by those dispicable persons to code their trash. It is an extremely easy way of diverting code execution to your own control and blah, blah, blah ...
... and everyone will think it contains a virus.
Paul
Because eflags and a few cpuid 'calls' gets you everything and a whole lot more than you'd want to print.
SEH would be quite a bit of overhead for this, especially when the 'information gathering' is pretty simple and linear.
Of course you are correct, Tedd, but I think the idea is to come up with another way besides using CPUID because it works inconsistantly across all machines. I, personally, do not know if there IS a better way but I think playing with the idea may be a great adventure for all of us.
Any ideas, JJ? I am certain you have been investigating this.
Paul
Perhaps some define masks could help
Quote
MaximumReturnValue equ 0 ;in eax,return max value accepted by eax
;cpuid with eax == 1
cpu_ecx_SSE3 equ 1 SHL 0
cpu_ecx_reserved1 equ 1 SHL 1
cpu_ecx_reserved2 equ 1 SHL 2
cpu_ecx_reserved3 equ 1 SHL 3
cpu_ecx_DS_CPL equ 1 SHL 4
cpu_ecx_VMX equ 1 SHL 5
cpu_ecx_SMX equ 1 SHL 6
cpu_ecx_EST equ 1 SHL 7
cpu_ecx_TM2 equ 1 SHL 8
cpu_ecx_SSSE3 equ 1 SHL 9
cpu_ecx_CNXT_ID equ 1 SHL 10
cpu_ecx_reserved11 equ 1 SHL 11
cpu_ecx_reserved12 equ 1 SHL 12
cpu_ecx_CMPXCHG16B equ 1 SHL 13
cpu_ecx_xTPR_Update equ 1 SHL 14
cpu_ecx_PDCM equ 1 SHL 15
cpu_ecx_reserved16 equ 1 SHL 16
cpu_ecx_reserved17 equ 1 SHL 17
cpu_ecx_DCA equ 1 SHL 18
cpu_ecx_SSE4_1 equ 1 SHL 19
cpu_ecx_SSE4_2 equ 1 SHL 20
cpu_ecx_x2APIC equ 1 SHL 21
cpu_ecx_MOVBE equ 1 SHL 22
cpu_ecx_POPCNT equ 1 SHL 23
cpu_ecx_Reserved24 equ 1 SHL 24
cpu_ecx_Reserved25 equ 1 SHL 25
cpu_ecx_XSAVE equ 1 SHL 26
cpu_ecx_OSXSAVE equ 1 SHL 27
cpu_ecx_Reserved28 equ 1 SHL 28
cpu_ecx_Reserved29 equ 1 SHL 29
cpu_ecx_Reserved30 equ 1 SHL 30
cpu_ecx_Reserved31 equ 1 SHL 31
;----------------------------------------
cpu_edx_FPU equ 1 SHL 0
cpu_edx_VME equ 1 SHL 1
cpu_edx_DE equ 1 SHL 2
cpu_edx_PSE equ 1 SHL 3
cpu_edx_TST equ 1 SHL 4
cpu_edx_MSR equ 1 SHL 5
cpu_edx_PAE equ 1 SHL 6
cpu_edx_MCE equ 1 SHL 7
cpu_edx_CX8 equ 1 SHL 8
cpu_edx_APIC equ 1 SHL 9
cpu_edx_Reserved10 equ 1 SHL 10
cpu_edx_SEP equ 1 SHL 11
cpu_edx_MTRR equ 1 SHL 12
cpu_edx_PGE equ 1 SHL 13
cpu_edx_MCA equ 1 SHL 14
cpu_edx_CMOV equ 1 SHL 15
cpu_edx_PAT equ 1 SHL 16
cpu_edx_PSE_36 equ 1 SHL 17
cpu_edx_PSN equ 1 SHL 18
cpu_edx_CLFSH equ 1 SHL 19
cpu_edx_Reserved20 equ 1 SHL 20
cpu_edx_DS equ 1 SHL 21
cpu_edx_ACPI equ 1 SHL 22
cpu_edx_MMX equ 1 SHL 23
cpu_edx_FXSR equ 1 SHL 24
cpu_edx_SSE equ 1 SHL 25
cpu_edx_SSE2 equ 1 SHL 26
cpu_edx_SS equ 1 SHL 27
cpu_edx_HTT equ 1 SHL 28
cpu_edx_TM equ 1 SHL 29
cpu_edx_Reserved30 equ 1 SHL 30
cpu_edx_PBE equ 1 SHL 31
sample
Quote
mov eax,MaximumReturnValue ; is cpuid support the 1 function ?
cpuid
.if eax >= 1
mov eax,1
cpuid
mov eax,0
test edx,cpu_edx_SSE2
jz @F
mov eax,1 ;support of sse2
@@:
test ecx,cpu_ecx_POPCNT
jz @F
inc eax ;support POCNT
@@:
.else
mov eax,0
.endif
For most practical applications, these lines should be sufficient...
include \masm32\include\masm32rt.inc
.code
start:
print "Supports SSE"
call ChkSSE2
print str$(eax)
exit
ChkSSE2 proc ; exactly 40 bytes with global return variable, 39 for ret eax
pushad
push 1
pop eax
db 0Fh, 0A2h ; cpuid 1
xor eax, eax
xor esi, esi
bt edx, 25 ; edx bit 25, SSE1
adc eax, esi
bt edx, 26 ; edx bit 26, SSE2
adc eax, esi
bt ecx, esi ; ecx bit 0, SSE3 (esi=0)
adc eax, esi
bt ecx, 9 ; ecx bit 9, SSE4
adc eax, esi
mov [esp+32-4], eax ; popped eax will contain the counter
; mov CpuSSE, eax ; optional: global return variable
popad
ret
ChkSSE2 endp
end start ; thanks, Herge ;-)
Hi jj2007:
Here's how I get the Intel Brand String.
.data
IntelString equ Iebx;
Iebx dd 0
Idcx dd 0
Iecx dd 0
dd 0 ; Zero Bytes
.code
Genuine proc uses esi ebx ecx
xor eax, eax
cpuid
mov esi, offset IntelString
mov DWORD ptr [ esi + 0 ], ebx ; "Gene"
mov DWORD ptr [ esi + 4 ], edx ; "ineI"
mov DWORD ptr [ esi + 8 ], ecx ; "ntel"
invoke StdOut, ADDR IntelString
ret
Genuine endp
Regards herge
Hi jj2007:
Results from my computer.
Supports SSE4
P.S. you fogot the
end start
Regards herge
I am using this type of chain per intel docu.
Can be extended to cover SSE II up.
regards,
Ficko
.model flat
; ===========================================================================
extrn _isse:byte
extrn _mmx:byte
extrn _processor:dword
.code
; Puts _isse = TRUE if ISSE Exists: _mmx = TRUE if MMX Exists and _processor = CPUID
; =============== S U B R O U T I N E =======================================
_getprocessor proc near public
;check_80386
pushfd ; push original EFLAGS
pop eax ; get original EFLAGS
mov ecx, eax ; save original EFLAGS
xor eax, 40000h ; flip AC bit in EFLAGS
push eax ; save new EFLAGS value on stack
popfd ; replace current EFLAGS value
pushfd ; get new EFLAGS
pop eax ; store new EFLAGS in EAX
xor eax, ecx ; can't toggle AC bit, processor=80386
jz end_cpu_type ; jump if 80386 processor
push ecx
popfd ; restore AC bit in EFLAGS first
;-------------------------------------------------------------------------------------
;check_80486 ; Intel486 processor check
; Checking for ability to set/clear ID flag (Bit 21) in EFLAGS
; which indicates the presence of a processor with the CPUID
; instruction.
mov eax, ecx ; get original EFLAGS
xor eax, 200000h ; flip ID bit in EFLAGS
push eax ; save new EFLAGS value on stack
popfd ; replace current EFLAGS value
pushfd ; get new EFLAGS
pop eax ; store new EFLAGS in EAX
xor eax, ecx ; can't toggle ID bit,
je end_cpu_type ; processor=80486
;-------------------------------------------------------------------------------------
;USE CPUID
xor eax, eax ; CPUID level 0
cpuid
dec eax ; make sure 1 is valid input for CPUID
jb Exit ; if not, jump to end
xor eax, eax
inc eax
cpuid ; EDX = feature flag
and edx, 800000h ; test bit 23 of feature flag
shr edx, 23
mov byte ptr ds:_mmx, dl
xor eax, eax
inc eax
cpuid
mov dword ptr ds:_processor, eax ; Store processor family/model/step
mov esi, edx ; Store features bits
mov eax, 80000000h
cpuid
;-------------------------------------------------------------------------------------
; Check which extended functions can be called
cmp eax, 80000001h ; Extended Feature Bits
jb no_ISSE ; jump if not supported
mov eax, 80000001h ; Select function 0x80000001
cpuid
mov edi, edx ; Store extended features bits
shr esi, 25
xchg eax, esi
and al, 1
jnz ExISSE
shr edi, 22
xchg eax, edi
and al, 1
jnz ExISSE
no_ISSE: xor eax, eax
jmp ExISSE
Exit:
xor eax, eax
end_cpu_type:
mov dword ptr ds:_processor, eax
mov byte ptr ds:_mmx, al
ExISSE: mov byte ptr ds:_isse, al
ret
_getprocessor endp
end
"There is one,in particular,that isn't shown by your prog.
Quote:
NUMBER_OF_PROCESSORS=1"
You can add info for cores too: :wink
Short version:
P3 (2000+), MMX, SSE3
Full version:
CPU family 6, model 7, P3 (2000+), MMX, SSE6
Step 6
Model 7
Family 6
Type 0
Ext model 1
Ext family 0
Cores 2
Manufacturer GenuineIntel
[attachment deleted by admin]
Quote from: Mark Jones on March 31, 2009, 05:18:41 AM
Quote from: lingo on March 31, 2009, 03:22:09 AM
... SSE6
Whoa, I need to upgrade. :bg
CPU family 6, model 14, Core (2006+), MMX, SSE
6I was upgraded, too - thanks, Lingo :cheekygreen:
Might want to check for 64 bit as well:
Test64bit:
.unknown
mov eax, 00000000h
cpuid
cmp eax, 00000000h
je >.amd
.intel
mov eax, 00000001h
cpuid
bt edx, 30
jc >.64bit
// 32 bit
xor eax,eax
ret
.amd
mov eax, 80000000h
cpuid
cmp eax, 80000000h
jbe >.32bit
mov eax, 80000001h
cpuid
bt edx, 29
jc >.64bit
.32bit
xor eax,eax
ret
.64bit
mov eax,1
ret
Quote from: Mark Jones on March 31, 2009, 05:18:41 AM
Quote from: lingo on March 31, 2009, 03:22:09 AM
... SSE6
Whoa, I need to upgrade. :bg
Hurry up, I suspect some members already arrive at SSE8!
If you want to slow down this incredible rate of progress, insert the following:
* Core 2 (2006): family 6, model 15 @
and CpuSSE, 0 .if family==5
...
Thanks, Lingo :thumbu
ID'ing the CPU (and in the old days, NDP) has gotten sloppier each time someone adds a device
One of the reasons is that mfg B does not care if they follow the rules set forth by mfg A
Another reason is that mfg A cannot predict the future, so find reasons to violate their own rules - lol
I can see how it could get messy
It is somewhat easier now than with the earlier processors
In some cases, we had to find code that executed differently on one CPU/NDP to ID it
.
.
.
this is a dual pentium machine...
Short version:
Pentium 4 Prescott (2005+), MMX, SSE3
Full version:
CPU family 15, model 4, Pentium 4 Prescott (2005+), MMX, SSE6
Step 3
Model 4
Family 15
Type 0
Ext model 0
Ext family 0
Cores 2
Manufacturer GenuineIntel