addressing scale factors

[asmfan]

Good day,
i wonder if using of scale factors (2/4/8) in indirect memory addressing is make sense?
e.g. is following code is better...
code:
mov    edi, ArrLen/8
@@:
movq    mm0, [ebx + edi*8 - 8]
;some processing
dec    edi
jnz    @B

...than
code:
mov    edi, ArrLen
@@:
movq    mm0, [ebx + edi - 8]
;some processing
sub    edi, 8
jnz    @B

I need pro and contra of using scale factors.

[hutch--]

Igor,

The scaling factor is always a single number, the addition integer is called a displacement which is simply an offset correction in either direction. It is a rather neat way to be able to address data and can be very useful.

The is an intel opcode that actually uses the displacement as the base address, you get it in the form,

[displacement+reg*scale]

It allows you to use the address of a table directly and just vary the index which must be a register.

I think to answer your question more directly, on later hardware, the more complex the addressing mode, the more work it takes but its a variable depending on what hardware you are using. Intel PIV tends to favour complex addressing where AMD tend to favour more instructions which are simpler but this very much depends on the specific hardware.

[asmfan]

thanks Steve, it explains a lot... but can we say that time of execution this instruction (generating address using scale factor) depends on processor architecture? P4 has a long execution unit(line-queue)(NetBurst) while AMD has short one. The new Intel's Conro will have the short one as P3 had and NetBurst will be forgotten... so we'll see the effectiveness of scale addressing on short lines...

[hutch--]

I will be interested to see what the new Intel stuff does as I found the PIII a lot easier to reliably code on than a PIV which has a few strange things you have to aviod. The PIII handles complex addressing modes very well and was fast with LEA which the PIV is not with. From the technical data I have seen recently the window of advantage with AMD will only last for about 6 more months as Intel have some fast stuff on the way and some very good chip sets with them.

From what I have heard AMD will still have the advantage with quad core processors but Intel have some dual core designs on the way that will outperform the matching AMD dual core designs. It still make assembler programming a brave new world and when the hardware and OS design catch up to the full potential of true 64 bit, correctly hand written code with all of the extra registers should be genuinely fast.

[Mark Jones]

[Multi-core architecture] still makes assembler programming a brave new world and when the hardware and OS design catch up to the full potential of true 64 bit, correctly hand written code with all of the extra registers should be genuinely fast.

Define "Genuinely Fast" in regards to four processors! :lol :U

It might be more of a challenge finding ways to slow down four processors. :toothy