questions with switching between 16-bit and 32-bit

[ninjarider]

im currently working on a boot loader and are wanting to take advantage of the extra power the 32-bit offers. i was wondering common ways of switching back and forth between the two and problems or conditions i should be aware of. i know i have the intel manual somewere but my computer at home is a piece of shit p3 laptop that nothing really works on and also the lack of access to the internet.

[Tedd]

If you want to avoid crashing the machine 6000 times without knowing why: take the trouble to get the manual. There is a whole section about switching 16-bit -> 32-bit (in steps!!) and the other way too.
Then when you've done it and it still crashes, you can come back and ask why (and maybe I won't tell you RTFM :bdg)

[ninjarider]

rtfm ???????

[zooba]

Read The ... err... Manual :toothy

[Tedd]

RTFM: Read The F**ing Fine Manual :bg

I'm not saying it to be mean - you'll just save yourself a whole heap of trouble by collecting a few information resources before starting (whichi s obviously why you're asking here :wink)

General info for switching to 32-bit mode (stolen directly from the intel system dev manual)

Switching to Protected Mode

Before switching to protected mode, a minimum set of system data structures and code modules
must be loaded into memory. Once these tables are created, software initialization code can
switch into protected mode.

Protected mode is entered by executing a MOV CR0 instruction that sets the PE flag in the CR0
register. (In the same instruction, the PG flag in register CR0 can be set to enable paging.)
Execution in protected mode begins with a CPL of 0.

The 32-bit Intel Architecture processors have slightly different requirements for switching to
protected mode. To insure upwards and downwards code compatibility with all 32-bit Intel
Architecture processors, it is recommended that the following steps be performed:

1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI
   interrupts can be disabled with external circuitry. (Software must guarantee that no
   exceptions or interrupts are generated during the mode switching operation.)

2. Execute the LGDT instruction to load the GDTR register with the base address of the
   GDT.

3. Execute a MOV CR0 instruction that sets the PE flag (and optionally the PG flag) in
   control register CR0.

4. Immediately following the MOV CR0 instruction, execute a far JMP or far CALL
   instruction. (This operation is typically a far jump or call to the next instruction in the
   instruction stream.)

   The JMP or CALL instruction immediately after the MOV CR0 instruction changes the
   flow of execution and serializes the processor.

   If paging is enabled, the code for the MOV CR0 instruction and the JMP or CALL
   instruction must come from a page that is identity mapped (that is, the linear address before
   the jump is the same as the physical address after paging and protected mode is enabled).
   The target instruction for the JMP or CALL instruction does not need to be identity
   mapped.

5. If a local descriptor table is going to be used, execute the LLDT instruction to load the
   segment selector for the LDT in the LDTR register.
    (The LDT is located in a system segment of the LDT type. The GDT must contain a segment
    descriptor for the LDT segment. If the system supports multiple LDTs, each must have a separate
    segment selector and segment descriptor in the GDT. The segment descriptor for an LDT
    can be located anywhere in the GDT.)

6. Execute the LTR instruction to load the task register with a segment selector to the initial
   protected-mode task or to a writable area of memory that can be used to store TSS
   information on a task switch.

7. After entering protected mode, the segment registers continue to hold the contents they had
   in real-address mode. The JMP or CALL instruction in step 4 resets the CS register.
   Perform one of the following operations to update the contents of the remaining segment
   registers.

   -- Reload segment registers DS, SS, ES, FS, and GS. If the ES, FS, and/or GS registers
      are not going to be used, load them with a null selector.

   -- Perform a JMP or CALL instruction to a new task, which automatically resets the
      values of the segment registers and branches to a new code segment.

8. Execute the LIDT instruction to load the IDTR register with the address and limit of the
   protected-mode IDT.

9. Execute the STI instruction to enable maskable hardware interrupts and perform the
   necessary hardware operation to enable NMI interrupts.

Random failures can occur if other instructions exist between steps 3 and 4 above. Failures will
be readily seen in some situations, such as when instructions that reference memory are inserted
between steps 3 and 4 while in System Management mode.

[ninjarider]

last time i remember reading the manual there was all these pictures and diagrams that made it not seem worth the time or effort of switching between modes. when i get my work computer setup the way its suppose to i am going to dl all the files again since i can't find them.