Still confused about paging

[AeroASM]

In PDEs and PTEs there is only 20 bits to store the physical address of the page. Is this the upper 20 bits of the actual physical address, and the lower 12 bits are zero?

In a linear address say 00401000, the index into the PD is the top ten bits, the index into the PT is the next ten bits and the offset within the page is the lower 12 bits. Therefore in the above example the MMU will use the first entry in the PD, first entry in the PT and it is at the beginning of the page. Is this correct? If several processes are using this same linear address, how does Windows stop clashes? Is the CR3 register changed on each task switch?

Thanks.

[The Dude of Dudes]

Hello AeroAsm!

I'm a little rusty (havent worked with PDE/PTE's for a bit).

CR3 contains the PHYSICAL address of the Page Directory, and it's value is changed every time Windows switches 'tasks' (Processes, really). In fact, the Kernel EPROCESS structures (Kernel objects that represent processes)  has a field that contains the CR3 value for each process. So no process can interfere with anothers memory directly.

10  bits represents 0-1024, so the Page Directory can have 1024 entries. The upper 10 bits represent an index into the Page Directory, to find the offset in the directory multiply by (sizeof DWORD). Here (in the PDE) you'll find the PHYSICAL address of the associated Page Table in the upper 20 bits, the lower 12 are flags. We only need the upper 20 because Page Tables are always aligned on 4k boundries. Once we have the PHYSICAL address of the needed Page Table, we take the next 10 bits of the virtual address we are translating and use it as an offset into the Page Table (* sizeof DWORD) and we get the PHYSICAL address of the associated virtual address. Again, the lower 12 bits are flags, but that's okay since Physical Pages are on 4k boundries. The lowest 12 bits of the virtual address are used as an offset into this Physical Page, and that's the PHYSICAL address that represents the VIRTUAL address. This is for x86 Small Pages (4k)

x86 Large Pages are much simpler. The Upper 10 bits in the Page Directory Entry represent the start of a 4mb page in PHYSICAL memory, and the lower 22 bits of the virtual address are an offset into this page. Thats the PHYSICAL address associated with the VIRTUAL address. Page size is determined by the Page Size bit (7) of all Page Directory entries. The system can mix large and small pages in the same Page Directory. Larger pages mean less translation = faster code, so on Windows systems with >256mb RAM the Kernel is mapped into large pages, while user code is mapped into small pages.

Hope this is of some help!
 

   The Dudeman