question about Selector Register

[MASM]

In Protected Mode Selector Registers are 16 bit wide and point to a Descriptor.

Does it mean my GDT has to be in the first 64kB of memory, because 64kB is as much as you can address with 16 bit?

I have a code which has a GDT at FFFF0000H.

I mean this is something which I have to adapt anyway, because I have no RAM near 4 GB.

However, I am still puzzled by a GDT at FFFF0000H, while the CS DS ES FS GS registers are only 16 bit.

[MASM]

Now I found another explanation but I don't know if it is right.

there is the LGDT directive which tells the system where the GDT is located.

I assume that the CS DS ES FS GS selectors add themselves to the GDT base address which is known from the LGDT directive.

In my code the LDGT directive is first then an MOV DS,10H instruction to let the DS selector point to the third descriptor in the table.

[bomz]

first GDT always in first 640 kb because you go to protected from real. 16 bit is only part of segment register which you may see.

LGDT directive which tells the system where the GDT is located.

GDTR register

http://www.masm32.com/board/index.php?topic=17944.msg151742#msg151742

[MASM]

so if a CS DS ES FS GS selector register is only 16 bit and the rest is hidden do I see the lower or upper 16 bits?

(my guess is the lower 16 bits)

what are the upper 16 bits made up from, then?

Please forgive me asking all these questions, but I need to understand what I am doing.

[dedndave]

in protected mode, the selector value indexes into the table
the 32-bit physical addresses are in the table
so, the selectors do not need to be very large

[MichaelW]

The "visible" part of the segment register contains a 16-bit segment selector in PM and a 16-bit segment address in RM. The "invisible" part of the segment register is a Segment Descriptor Cache.

[bomz]

You can't use hidden part of segment register. You only may know about it.

Segment Register 16 bit contain NUMBER from GDT table
GDTR register contain pointer to GDTable in Memory
GDTable may address 4 G

So to point 4 G memory you need in segment register only number 16 bit more than need for this

[MichaelW]

You can't use hidden part of segment register. You only may know about it.

The values that get loaded into the descriptor cache are the values that you specify in your segment descriptor. I would call this a "use" of the descriptor cache.