Standardization of x86 instruction set

[bozo]

I've always wondered why Intel never implemented vector rotate and vector conditional move instructions for their cpus as these can be extremely useful for certain operations, particularly cryptography.

For vector conditional moves, IBM have VSEL, STI have SELB in (Cell B.E) and now AMD will have VPCMOV in bulldozer due for release this year...but intel still refuse to implement something similar and it looks like we're going to have another instruction set war between AMD/INTEL which benefits no one really, just creates headaches for developers who have to write separate code for each.

should there be a standardization of instruction sets or would this never work?

MOD: not sure where this discussion would go...feel free to move.

[donkey]

Agner discussed this kind of thing in his blog some time ago

Stop the instruction set war

[hutch--]

I would not hold your breath on getting any form of agreement between AMD and Intel over instruction sets as Intel will never share their market with AMD or support any initiatives introduced by AMD. The problem has been that when AMD try and lead with design changes Intel do not follow and do their own design changes (extra instructions) by their own criterion with no thought as to the interests of AMD.

[FORTRANS]

<snip> Intel do not follow and do their own design changes (extra instructions) by their own criterion with no thought as to the interests of AMD.

Hi,

   The problem with Intel is they do things with no thought to
the interests of the end user.

Regards,

Steve N.

[hutch--]

Steve,

Its probably the case that Intel have no thought for the AMD end user. Both AMD and Intel play one upmanship, its just that Intel are bigger and better at it.

[Farabi]

They should map the opcode to a 4 byte per instruction, it should be enough at least a decade it they did not waste it.