Intel specific instruction set recognition.

[hutch--]

 :bg

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! and rax, 0000000000000000000000000000000000000000000000000000000000000001b


[hutch--]

Dave,

would you give this a whirl on your 3 gig Prescott with XP. Its a logical core count that works OK on both quads but reports 1 core on the PIV as it has win2000 with hyperthreading disabled. If I have it right on an OS that enables hyperthreading it should show 2 logical cores.

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IF 0  ; ¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤
                      Build this template with "CONSOLE ASSEMBLE AND LINK"
ENDIF ; ¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤

    include \masm32\include\masm32rt.inc

    .code

start:
   
; ¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤

    call main
    inkey
    exit

; ¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤

main proc

    call logical_core_count
    print str$(eax)," logical cores",13,10

    ret

main endp

; ¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤

logical_core_count proc

    mov eax, 4
    mov ecx, 0
    cpuid

    shr eax, 26
    add eax, 1                ; correct for zero base

    ret

logical_core_count endp

; ¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤¤

end start


[dedndave]

after the include, i had to add...

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.586

so it would allow CPUID

it reports...

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1 logical cores

enumerating the cores is a little bit involved - lol
the easy way is to grab GetProcessAffinityMask and count SystemAffinityMask bits   :P
but, that doesn't tell you cores per package
at the moment, i have my other drive removed to do something else - later today, i will find some code....

[hutch--]

DSave,

The thing I need that does not appear all that easy to find is the physical core count. I have climbed through CPUID documentation and there is little there of any use to do this. I had a preference to get it direct from the processor rather than the OS but getting the physical core count is useful in high performance multi-thread code.

[dedndave]

yah - that is where it gets a little tricky   :bg

first - only Intel chips have hyper-threading
if you go to (near) the end of their CPUID documentation, there is a paragraph that explains it

for any other manufacturer, the physical core count is the logical core count

[Siekmanski]

I had the same with my netbook dualcore....
1 instead of 2 processors.

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mov    eax,1
cpuid
shr    ebx,16
and    ebx,255
mov    dwProcessorCount,ebx


Now it shows 2 processors

[dedndave]

it depends on how the programmer that wrote the routine defines processor cores
i have a similar processor - a prescott
it is 1 package with 1 physical processor, but 2 logical cores
this is intel's HTT - hyperthreading technology
it uses a single processor core to run 2 threads at the same time
well - not exactly the same time - lol
i think it involves something like running one thread on the negative clock edges and another on the positive clock edges
that is probably a bit simplified, but you get the idea

[hutch--]

The mechanism is pretty straight forward, Intel hyperthreading was a single core with faster task switching. Order of about 30% improvement from the data I have read. The Core2 Quad has 4 physical cores but no hyperthreading where the i7 Quad has 4 cores with hyperthreading which gives it a logical core count of 8. I will have to test the algo on the PIV after I enable hyperthreading in the BIOS, Win2000 does not run it properly and reports 2 processors but it may resolve the difference.

[clive]

While I think bi-phased and/or multi-phased clocks are probably used within the design (like double clocked ALU), the hyperthreading is using standard resources to dispatch as many instructions to as many available execution units as possible in a common clock domain. The system has additional register banks to hold the multiple contexts (visible registers, flags, etc), but they share a pool of registers used by the renaming/retire unit, and feeding the execution units. The threads share the cache(s), bus, instruction fetching, write buffers, branch predictions, etc.

There is arbitration between the instruction streams so one stream does not hog all the resources (the sort of ping-pong Dave infers), but one stream is unlikely to saturate all the execution units within the device. The execution units have pipelined stages so a new function can typically be initiated on each unit at every cycle. If one stream stalls with a dependency, the other takes up the slack. If both are going full bore there is going to be some fighting/sharing or resources.

Using hyperthreading can slow down tasks as the available resources have not been doubled, and must be shared by the threads. There are however more execution units than can be saturated by a single thread.