SHLD/SHRD lesson (quirk)

[dedndave]

i thought if you SHR a reg32 by a count of 32, it goes to 0
nope
BUT !
here is a little goodie i didn't know (until now) - lol...

mov edx,0FFFFFFFFh
mov eax,0
shrd edx,eax,31
print uhex$(edx),13,10   ;00000001

mov edx,0FFFFFFFFh
mov eax,0
shrd edx,eax,32
print uhex$(edx),13,10   ;FFFFFFFF

the results are the same if i put the count in CL
it acts as though the count is AND'ed with 31 before the shift

[sinsi]

Read those manuals, dave  :bg

The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The count range is limited to 0 to 31 (or 63 if 64-bit mode and REX.W is used).

[dedndave]

yah - i know - it is easier to write the code than it is to find the dang thing in a PDF - lol
for single registers - it is ok
but, for SHRD and SHLD, that 32nd shift could have meaning
i am using it in a case where the shift count is calculated in CL, of course

[sinsi]

That was one way of distinguishing an 80186 processor from an 8086 - the 8086 didn't mask the shift count but the 80186 did.

You can shrd with a count ot 32 - look up "mov"  :bdg

[dedndave]

unfortunately, you can't calculate a mov in CL - lol
it's not a problem - the solution is simple - make a shift of 0 a valid answer
i didn't find it by debugging a program
i wrote the code above to test it, first   :U