can't assemble a simple instruction

[ramguru]

from intel manual:

MOVQ r/m64,xmm   |    Move quadword from xmm register to r/m64.

r/m64 — A quadword general-purpose register or memory operand used for
instructions whose operand-size attribute is 64 bits when using REX.W.
Quadword general-purpose registers are: RAX, RBX, RCX, RDX, RDI, RSI, RBP,
RSP, R8–R15; these are available only in 64-bit mode. The contents of memory
are found at the address provided by the effective address computation.

my code:

Code Select Expand


movq   rcx, xmm1


assembler error:

Error!
..
Invalid operand for this mnemonic:-
movq   rcx, xmm1

Don't say I'm the first to use such "complex" instruction & that it's a bug...

[1rDirEctoALgran0]

Simple question : Do you used x86 or x64 option in the command line ?

Patrick

[ramguru]

My whole development environment is tuned for x64 platform now :} (well mostly *.bat files) so don't worry 'bout that
Also there is a problem with (throws an error):

Code Select Expand


mov    r8l, [rsi+rcx+1]
mov    B[rdi], r8l

but instead

Code Select Expand


mov    al, [rsi+rcx+1]
mov    B[rdi], al

compiles fine


maybe in goasm r8l = r8b .. but that's not Intel's notation

[qWord]

hi,

the movq instruction (SSE2) supports only mmx/xmm registers  and mem64 -> use movd

regards, qWord

[dedndave]

do you need a .MMX directive, perhaps ?

[1rDirEctoALgran0]

qWord is true, you can't use rcx with movq.
And what is r8l ?
Only r8b, r8w, r8d and r8 are allowed.

Patrick

[ramguru]

Then how come Intel manual 253666.pdf (3-660 Vol. 2A) says
there is such instruction (who lie?):

66 REX.W 0F 7E /r MOVQ r/m64, xmm Valid N.E. Move quadword from xmm register to r/m64.

And r8l is Intel's valid notation for r8 register's 8 least significant bits .. not r8b

and existence of such inst. really would make sense:
movq -> move quadword.
rcx -> quadword
movq rcx, xmm1 -> sends lower 64 xmm1 bits to rcx register 

[qWord]

hi,

you're right, Intel's documents are a bit confusing. You can find two entry's for movq in Vol 2A:  "MOVD/MOVQ—Move Doubleword/Move Quadword" and "MOVQ—Move Quadword"  (AMD's documents are much more clear in this point).
The first uses GPR's while the second only supports mmx/xmm registers. In the former case, the only difference between movd and movq is the REX.w prefix - that may be the reason why goasm (and masm) doesn't like such use of movq.

regards, qWord

[1rDirEctoALgran0]

Conclusion ?

movq rcx, xmm1 ; this instruction must be implemented in GoAsm.  :'(
r8l ; this mnemonic must be implemented in GoAsm. (r0, r1, r2,... also)  :'(

Patrick

[ramguru]

My conclusion is if:
movd rcx, xmm1 really does the job -
send 64 bits from xmm register then that's ok with me.
And regarding r8l .. r15l - that's Intel's notation
and r8b .. r15b - that's AMD notation (i didn't know earlier).
So I can live with r8b - no big deal.

[1rDirEctoALgran0]

My conclusion is if:
movd rcx, xmm1 really does the job -
send 64 bits from xmm register then that's ok with me.

but >>> send 32 bits from xmm register.
Yes, you can insert the rex byte before the instruction to change it to 64 bits.  :tdown
Jeremy : Can you implement a normal syntax ?  ::)

Patrick

[jorgon]

Hi all

I'll look into this and come back to you.

[Yuri]

Hi Jeremy,

When using FPU, I noticed that the FISTTP instruction is not supported by GoAsm. Not a big deal, of course, but I think it could be convenient sometimes. What is your opinion on that?

FISTTP — Store Integer with Truncation

Opcode Instruction 64-Bit Mode Compat/Leg Mode Description

DF /1  FISTTP m16int Valid Valid Store ST(0) in m16int with truncation.

DB /1  FISTTP m32int Valid Valid Store ST(0) in m32int with truncation.

DD /1  FISTTP m64int Valid Valid Store ST(0) in m64int with truncation.

[Mark Jones]

FISTTP appears to be SSE3.

Personally, I decided against asking Jeremy if he could add this because programming for windows is already so abstract and convoluted. Many PC's still do not support SSE3, so any code we plan on releasing will require coding earlier extension versions as well.

If you wanted to try the FISTTP instruction literally, see the bottom here:
http://www.ray.masmcode.com/tutorial/fpuchap5.htm

[Yuri]

Oh, thanks for the info, Mark. I would have never thought it's somehow connected to SSE3. Then I think you are right. It's useless even for me because of my Athlon XP.